SN65HVD1050QDRQ1

Kujtim,

Can you lower the voltage resolution on the CANH and CANL plots and place the cursors at the same level? I can't exactly tell what is happening in these screenshots.

To answer your question, some overshoot can be normal depending on bus topology (cable length, amount of nodes). This can be the result of mismatched impedances, inductance from the cable, or added inductance + capacitance from passive components on the bus.

As for the artifacts, the on that catches my attention is the almost square wave at the end of the second screenshot, when is this occurring? I know you said startup, but is this before the rest of the device fully powers on?

Regards,

Eric Hackett 

I just noticed your question about C607. The upper limit is 100nF.

Regards,

Eric Hackett

Kujtim,

Usually, we see a range of 4.7 nF to 100 nF for the split termination capacitor, which is why Eric is recommending 100 nF as a maximum. The tradeoff with additional capacitance, in theory, could be slightly slower edges on the dominant-to-recessive transition.

Best,

Danny