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TLK6002: TLK6002 MDIO Programming using Scripts

Part Number: TLK6002
Other Parts Discussed in Thread: CDCM6208

Sir

We could able to read and write the TLK6002 Register using MDIO interface.

As per the MDIO Software user guide (SLLU195–November 2013) , there are some device initialization scripts are used along with MDIO GUI software.

Query

Shall I get these scripts file to perform Various operations like Loop back, transmit and receive? Where it is available?

Regards

Ramesh 

  • @Rodrigo Natal

    Hi,

    I want to conduct shallow loop back test.

    Configuration 

    PRBS_EN                    ----  HIGH

    CODEA_EN                 ---- HIGH

    CODEB_EN                 --- HIGH

    PLL_LOCK failure is coming as LOW

    Pls suggest

    Regards

    Ramesh

  • Hi Ramesh,

    Unfortunately I could not locate any specific configuration scripts for this device.  I think our best option is to follow the recommendations from the datasheet and register map within it in order to configure the device.

    Are you testing using an EVM?  What is the reference clock frequency?  What data rate have you configured the device for?

    Shallow local loopback can be enabled by setting register 0x07[0]=1.

    Thanks,
    Drew

  • Dear Drew Miller

    A) Pls find the Answer

    1) Are you testing using an EVM?

    NO. We are using custom Board design by Us.

    2) What is the reference clock frequency? 

    153.6 MHZ

    3) What data rate have you configured the device for?

    Half Rate

    B) Similarly We kept the Pin Configuration as below

    C) We are following Datasheet Page 81

    4.19 JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES

    D) Findings from the experiments

     then scan the status register (0x05) , We have seen PLL locked bit set.

    Query

    1) Shallow loop back is working

    Shallow Local Loop back : ( register 7.0)

    2) We want to do remote deep loop back using fibre cable connecting transmitter to receiver .

    But , it is showing following status ( 0x05) : 0x71C9

                                       Error Count      (0x0E)  :0xFFFF

    3)Can we enable ARS during Shallow remote loop back test?

    Pls suggest

    Regards

    Ramesh

  • Hi Ramesh,

    Reading over the ARS part of the datasheet, it seems primarily dependent on the 8b/10b encoder.  I would expect that ARS could be enabled during shallow remote loop back test.  However, if for some reason this doesn't work, I would recommend testing with deep local loopback.

    I'm a bit confused about your loopback configuration.  You mentioned you wanted to do deep remote loopback, but then also have an external fiber cable loopback.  Can you clarify where the data is coming from in this loopback test?

    Thanks,

    Drew

  • Dear Drew Miller1,

    Ans to Para 1)

    While doing Loop back  Experiment - DEEP_LOCAL_LPBK , We have enabled the ARS. But test is failed after enabling ARS.

    It seems ARS is not applicable while doing loop back. Pls confirm if you have Eval board in your End to create strong point.

    Ans to Para 2)

    If you refer my figure below, BLUE Arrow path is showing starting and end point outside the IC boundary.

    So, We connected fiber to loop back the transmitted pattern data ( during loop back test ) to Receiver. otherwise RED line shown in figure is might be connecting transmitter data to receiver by IC itself.

    Query

    We have conducted several test. All are recorded and presented here for your persual

    Pls help us tune the signaling of SERDES

    Regards

    Ramesh

  • Dear Drew Miller1

    In your EVM TLK6002 also, Is this same behaviors appears?

    Could you pls help,

    Regards

    Ramesh

  • Hi Ramesh,

    Apologies for the delay.  Unfortunately, I do not have a TLK6002 EVM on hand, so it would be challenging for me to replicate this.

    While doing Loop back  Experiment - DEEP_LOCAL_LPBK , We have enabled the ARS. But test is failed after enabling ARS.

    It seems ARS is not applicable while doing loop back.

    Based on your observations, it seems I was incorrect regarding dependencies for ARS.

    Thanks for sharing a table of your observations.  It seems odd that there is a pattern dependency for the deep and shallow local loopback configurations.  For patterns which function in deep loopback, do these work if you disable loopback mode and instead have an external loopback?

    In order to verify HS link is functioning, I would recommend following 4.19.2 of the datasheet.  This will enable PRBS generation and verification on the serial links.  In order to test this, external loopback will be necessary, as shown below.  Please let me know if you are able to successfully link with this configuration.

    Thanks,
    Drew

  • Dear Drew Miller1

    Setup

    Setup is made as per above diagram mentioned by you.

    We are following as per the TLK6002 datasheet section 4.18.1 20-Bit Interface Mode (8b/10b Encoder/Decoder Disabled) (All CPRI/OBSAI Rates)

    a) We are sending continuously the Data via 20 bit  TDA external interface port.

    b)  we are looping back the  transmitted serial data to receiver port using fiber cable.

    Channel synchronization ( 5.2)  is not achieved.

    TX_FIFO_UNDERFLOW(5.7) & TX_FIFO_OVERFLOW (5.6) are being set.

    Status of all the register are recorded for your perusal.

    REG 0  (ADD :0x00) Data : 0x0E00

    REG 1  (ADD :0x01) Data : 0x010D

    REG 2  (ADD :0x02) Data : 0x000A

    REG 3 (ADD :0x03) Data : 0x01A3

    REG 4 (ADD :0x04) Data: 0x0000

    REG 5 (ADD :0x05) Data: 0x61C9

    REG 6 (ADD :0x06) Data: 0x C700

    REG 7 (ADD :0x07) Data: 0x 07C1

    REG 8 (ADD :0x08) Data: 0x354C

    REG 9 (ADD :0x09) Data: 0x0000

    REG 10 (ADD :0x0A) Data: 0x0800

    REG 11 (ADD :0x0B) Data:0x7FFF

    REG 12 (ADD :0x0C) Data: 0xFFFF

    REG 13 (ADD :0x0D) Data:0x 3000

    REG 14 (ADD :0x0E) Data:0xFFFF

    REG 15 (ADD :0x0F) Data: 0x1315

    REG 16 (ADD :0x10) Data: 0x0000

    REG 17 (ADD :0x11) Data: 0x0000

    REG 18 (ADD :0x12) Data: 0x0000

    REG 19 (ADD :0x13) Data: 0x0200

    REG 20 (ADD :0x14) Data: 0x7C4F

    REG 21 (ADD :0x15) Data: 0x0023

    REG 32 (ADD :0x20) Data: 0x0E00

    Query

    1) How to achieve channel synchronization?

    2) Can we get some help from SWAT Team (HSI) for any  TLK6002 EVM? . As it is internal to TI, it is easy to get for you.

    We are in critical situation. Pls help us.

    Regards

    Ramesh

  • Hi Ramesh,

    Apologies for the delay, I was out of office last week.  I will get back to you with a more detailed response tomorrow.

    Thanks,
    Drew

  • Dear Drew Miller1

    We have kept TX Clock and REF clock - Both @ 122.88.using CDCM6208

    Then, Line Rate Half, But Receiver clock is not Building Up

    Pls Suggest

    Regards

    Ramesh

  • Hi Ramesh,

    Sorry for the delay.

    Can we get some help from SWAT Team (HSI) for any  TLK6002 EVM? . As it is internal to TI, it is easy to get for you.

    Unfortunately, as far as I know, HSI team does not exist anymore.

    Do you have any output from the receiver clock?  If so, can you provide details.

    Thanks for sharing your register settings.  I have reviewed them and have some comments.

    • Can you confirm that your clock input is on REFCLK0?
    • I noted that in register 0x03, there is a mismatch between TX_SYMBOL_ORDER and RX_SYMBOL_ORDER.  Is there a particular reason why these are not matched?
    • Is there any change in behavior if CDRTHR is left at default?
    • Can you confirm your serial data rate and REFCLK rate?  I see 153.6 MHz is selected, but in the most recent response, looks like you're using 122.88 MHz.
    • You currently are sampling data on the falling edge.  Is this consistent with whatever device you're using to transmit/receive data?

    In order to achieve channel synchronization, it is important to include comma symbols in your data.  Are you doing this?  What is your test data pattern?

    Thanks,

    Drew