Other Parts Discussed in Thread: SN65DP141
Hi,
I'm building a 8.1Gbps DisplayPort TX+RX system, and 3m cable is used to transmit the signal.
TDP142 Re-driver is added to both ends of cable, but I found the re-driver at RX side adds jitter to eye diagram, cause limited margin of jitter.
It seems high frequency 0-1-0-1 pattern and low frequency 0-0-1-1 pattern triggers TDP142 pre-emphasis at different time.
Do you have any idea on the part I should look into? Or should I try SN65DP141 as it support UHBR signal rate? Thanks!
Below is the eye diagram I measured:
1) FPGA -> TDP142 @ TX -> 3m cable -> measurement
2) FPGA -> TDP142 @ TX -> 3m cable -> TDP142 @ RX(EQ set to 15) -> measurement
Two config use same setup for TX side, only difference is re-driver @ RX or not.
Thanks!
-Zhiwei