DS90UB954-Q1: [zhangyazhuan]how to configure mipi speed and mipi clk

Hello,

Thank you for your question and providing your setup. Looking at register 0x33 it appears that 2 lanes are being configured. Are you saying that you are seeing output on all 4 lanes even with 2 lanes configured? I will look over the pat gen registers you have provided and let you know if any need to be updated for your system. When you say per line clk rate, are you asking how to set the mipi clock speed or the data rate per lane?

Regards,

Darrah

Hello,

Currently you have indirect register 0x03 set to 0x24 which is the identifying value for RGB888 data, for RAW10 this value should be updated to 0x2B. Using the resolution you provided for RAW10 data this means line size would be 1600 bytes and the corresponding registers would be 0x04 = 0x06 and 0x05 = 0x40. The bar size would be 200 bytes corresponding to registers 0x06 = 0x00 and 0x07 = 0xC8.

I noticed that some of these register values are referenced in the comments. Are you setting up patgen using the register values you have listed or the highlighted comments?

Could you confirm your blanking parameters? Particularly the vertical front porch, vertical back porch, and vertical sync. 

hi，

we have resoloved this using raw 12 . thanks for your support.

Now we are using coax to connect 953 with 954 to generate test mode.

Could you pls provide some initial registers to generate this mode?

Also,could you pls provide some step to check and debug method step by step?

Hi,

Today,we we dumped all the registers .The third line.0x4e and 0x4 is abnormal compared with the second line.

We measure the pass and lock pin.

the blue one is the pass pin.

Could you provide some suggestion to solve this issue?

0x0 68 7a
0x7b 0 ff
0x75 0 f4
0x4e 4 eb
0xd b9 9
0x5c b0 18
0x5b b0 30
0xbc 0 80
0x5e 6c 0
0x66 6c 0
0x7c 81 20
0x76 0 55
0xb8 ac f8
0x5d 48 18
0x65 48 18
0x4f 2a 0
0x33 3 23
0xb0 1c 0
0xd3 3 1f
0xb2 1f a
0x20 20 30
0x7a 0 f
0x4d 3 10
0x70 1e 2b
0x4 df d7
0x58 58 5e
0x74 0 5
0xe 8 4
0x53 0 4
0xb1 13 f
0x1f 6 3
0x6d 7f 7c
0xc 81 83
0x35 1 0
0xa5 18 19
0x1 0 0
0x2 1e 1e
0x3 20 20
0x5 1 1
0x6 0 0
0x7 fe fe
0x8 1c 1c
0x9 10 10
0xa 7a 7a
0xb 7a 7a
0xf 7f 7f
0x10 0 0
0x11 0 0
0x12 0 0
0x13 0 0
0x14 0 0
0x15 0 0
0x16 0 0
0x17 0 0
0x18 0 0
0x19 0 0
0x1a 0 0
0x1b 0 0
0x1c 0 0
0x1d 0 0
0x1e 4 4
0x21 1 1
0x22 0 0
0x23 0 0
0x24 0 0
0x25 0 0
0x26 0 0
0x27 0 0
0x28 0 0
0x29 0 0
0x2a 0 0
0x2b 0 0
0x2c 0 0
0x2d 0 0
0x2e 0 0
0x2f 0 0
0x30 0 0
0x31 0 0
0x32 0 0
0x34 40 40
0x36 0 0
0x37 0 0
0x38 0 0
0x39 0 0
0x3a 0 0
0x3b 1 1
0x3c 14 14
0x3d 6f 6f
0x3e 0 0
0x3f 40 40
0x40 0 0
0x41 a7 a7
0x42 71 71
0x43 1 1
0x44 0 0
0x45 0 0
0x46 0 0
0x47 0 0
0x48 0 0
0x49 0 0
0x4a 0 0
0x4b 12 12
0x4c 1 1
0x50 0 0
0x51 0 0
0x52 0 0
0x54 0 0
0x55 0 0
0x56 0 0
0x57 0 0
0x59 0 0
0x5a 0 0
0x5f 0 0
0x60 0 0
0x61 0 0
0x62 0 0
0x63 0 0
0x64 0 0
0x67 0 0
0x68 0 0
0x69 0 0
0x6a 0 0
0x6b 0 0
0x6c 0 0
0x6e 88 88
0x6f 88 88
0x71 2c 2c
0x72 e4 e4
0x73 0 0
0x77 c5 c5
0x78 0 0
0x79 1 1
0x7d 0 0
0x7e 0 0
0x7f 0 0
0x80 0 0
0x81 0 0
0x82 0 0
0x83 0 0
0x84 0 0
0x85 0 0
0x86 0 0
0x87 0 0
0x88 0 0
0x89 0 0
0x8a 0 0
0x8b 0 0
0x8c 0 0
0x8d 0 0
0x8e 0 0
0x8f 0 0
0x90 0 0
0x91 0 0
0x92 0 0
0x93 0 0
0x94 0 0
0x95 0 0
0x96 0 0
0x97 0 0
0x98 0 0
0x99 0 0
0x9a 0 0
0x9b 0 0
0x9c 0 0
0x9d 0 0
0x9e 0 0
0x9f 0 0
0xa0 2 2
0xa1 f f
0xa2 0 0
0xa3 0 0
0xa4 8 8
0xa6 0 0
0xa7 0 0
0xa8 0 0
0xa9 0 0
0xaa 0 0
0xab 0 0
0xac 0 0
0xad 0 0
0xae 0 0
0xaf 0 0
0xb3 8 8
0xb4 25 25
0xb5 0 0
0xb6 18 18
0xb7 0 0
0xb9 33 33
0xba 83 83
0xbb 74 74
0xbd 0 0
0xbe 0 0
0xbf 0 0
0xc0 0 0
0xc1 0 0
0xc2 0 0
0xc3 0 0
0xc4 0 0
0xc5 0 0
0xc6 0 0
0xc7 0 0
0xc8 0 0
0xc9 0 0
0xca 0 0
0xcb 0 0
0xcc 0 0
0xcd 0 0
0xce 0 0
0xcf 0 0
0xd0 0 0
0xd1 43 43
0xd2 94 94
0xd4 60 60
f2

0x0 68 7a
0x7b 0 ff
0x75 0 f4
0x4e 4 eb
0xd b9 9
0x5c b0 18
0x5b b0 30
0xbc 0 80
0x5e 6c 0
0x66 6c 0
0x7c 81 20
0x76 0 55
0xb8 ac f8
0x5d 48 18
0x65 48 18
0x4f 2a 0
0x33 3 23
0xb0 1c 0
0xd3 3 1f
0xb2 1f a
0x20 20 30
0x7a 0 f
0x4d 3 10
0x70 1e 2b
0x4 df d7
0x58 58 5e
0x74 0 5
0xe 8 4
0x53 0 4
0xb1 13 f
0x1f 6 3
0x6d 7f 7c
0xc 81 83
0x35 1 0
0xa5 18 19
0x1 0 0
0x2 1e 1e
0x3 20 20
0x5 1 1
0x6 0 0
0x7 fe fe
0x8 1c 1c
0x9 10 10
0xa 7a 7a
0xb 7a 7a
0xf 7f 7f
0x10 0 0
0x11 0 0
0x12 0 0
0x13 0 0
0x14 0 0
0x15 0 0
0x16 0 0
0x17 0 0
0x18 0 0
0x19 0 0
0x1a 0 0
0x1b 0 0
0x1c 0 0
0x1d 0 0
0x1e 4 4
0x21 1 1
0x22 0 0
0x23 0 0
0x24 0 0
0x25 0 0
0x26 0 0
0x27 0 0
0x28 0 0
0x29 0 0
0x2a 0 0
0x2b 0 0
0x2c 0 0
0x2d 0 0
0x2e 0 0
0x2f 0 0
0x30 0 0
0x31 0 0
0x32 0 0
0x34 40 40
0x36 0 0
0x37 0 0
0x38 0 0
0x39 0 0
0x3a 0 0
0x3b 1 1
0x3c 14 14
0x3d 6f 6f
0x3e 0 0
0x3f 40 40
0x40 0 0
0x41 a7 a7
0x42 71 71
0x43 1 1
0x44 0 0
0x45 0 0
0x46 0 0
0x47 0 0
0x48 0 0
0x49 0 0
0x4a 0 0
0x4b 12 12
0x4c 1 1
0x50 0 0
0x51 0 0
0x52 0 0
0x54 0 0
0x55 0 0
0x56 0 0
0x57 0 0
0x59 0 0
0x5a 0 0
0x5f 0 0
0x60 0 0
0x61 0 0
0x62 0 0
0x63 0 0
0x64 0 0
0x67 0 0
0x68 0 0
0x69 0 0
0x6a 0 0
0x6b 0 0
0x6c 0 0
0x6e 88 88
0x6f 88 88
0x71 2c 2c
0x72 e4 e4
0x73 0 0
0x77 c5 c5
0x78 0 0
0x79 1 1
0x7d 0 0
0x7e 0 0
0x7f 0 0
0x80 0 0
0x81 0 0
0x82 0 0
0x83 0 0
0x84 0 0
0x85 0 0
0x86 0 0
0x87 0 0
0x88 0 0
0x89 0 0
0x8a 0 0
0x8b 0 0
0x8c 0 0
0x8d 0 0
0x8e 0 0
0x8f 0 0
0x90 0 0
0x91 0 0
0x92 0 0
0x93 0 0
0x94 0 0
0x95 0 0
0x96 0 0
0x97 0 0
0x98 0 0
0x99 0 0
0x9a 0 0
0x9b 0 0
0x9c 0 0
0x9d 0 0
0x9e 0 0
0x9f 0 0
0xa0 2 2
0xa1 f f
0xa2 0 0
0xa3 0 0
0xa4 8 8
0xa6 0 0
0xa7 0 0
0xa8 0 0
0xa9 0 0
0xaa 0 0
0xab 0 0
0xac 0 0
0xad 0 0
0xae 0 0
0xaf 0 0
0xb3 8 8
0xb4 25 25
0xb5 0 0
0xb6 18 18
0xb7 0 0
0xb9 33 33
0xba 83 83
0xbb 74 74
0xbd 0 0
0xbe 0 0
0xbf 0 0
0xc0 0 0
0xc1 0 0
0xc2 0 0
0xc3 0 0
0xc4 0 0
0xc5 0 0
0xc6 0 0
0xc7 0 0
0xc8 0 0
0xc9 0 0
0xca 0 0
0xcb 0 0
0xcc 0 0
0xcd 0 0
0xce 0 0
0xcf 0 0
0xd0 0 0
0xd1 43 43
0xd2 94 94
0xd4 60 60
f2

I checked the hardware  design. 954 uses the ext 50Mh osc and 953 uses the ext 25Mh osc. The mode is CSI MODE non-sychronous.

So I am wondering it is reasonable or not.

Hi ,

Newest  update is that when only generate 954 the pass and clock signal is high continously.

When setting register 0X58 from 0X1a to 0X9a or ox5a. The signal will become abnormal again.

Hello,

Glad to hear that the pat gen issue is resolved. This video, which goes over all of the diagnostics and built in checks of the devices, should be useful.

Can you explain the differences between the two rows and the different sets of registers you have posted? Are these all showing the same thing or have settings been changed?

In regards to the oscillators the 954 requires a 23-26 MHz reference clock. The 50 MHz is outside of this range and is not supported, this is likely the reason why you are seeing abnormal behavior. Please update the refclk signal to be between 23 and 26 MHz.

hi,

I got something wrong with the osc. 954 uses the ext 25Mh osc and 953 uses the ext 50Mh osc. 

Okay those oscillators will work. Could you explain the difference between the sets of registers you have posted, are they for the same set up? What abnormal behavior are you seeing? Is lock unstable?

Hi Darrah, below is the important difference:

1.0X4e register bit1 always shows cable fault

2.0x4 sometimes will be 0xd3,sometimes will be 0xdf，which shows the lock and pass  signals sometimes are low and sometimes are high, which is unstable.

3.Thirdly, when writing 0x5e to register 0x58. the lock and pass signal will be low completely.

So we dump the registers for your refenrence to diagnose the cause.

Besides writing to register 0x58, is there any difference between the register values in column 2 and column 3? I want to make sure that there aren't any other variables such as the set up that could be causing the instability. It looks like column 2 has an STP configuration and column 1 has coax. Did the two columns come from the same devices? Have you verified that there is not a cable fault anywhere?

Setting register 0x58 to 0x5e will set the back channel to 50 Mbps, which is for synchronous mode. Since you are using nonsynchronous mode, the back channel will need to be 10 Mbps, which means the register value should be 0x58[2:0] = 010.