SN65DSI83: test pattern question

BTW, how REFCLK is generated if using:

HS_CLK_SRC
0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous
clock

Dennis

Can you please share your schematic and the LVDS panel spec? 

Thanks

David

Hi, David,

I do not have schematics from the project, but from what I discuss: it looks REFCLK is connected to GND, so I have to use MIPI DSI clock.

I test to use DSI tuner as below:

below is tuner export and LVDS panel spec.

tuner-and-LVDS-spec.zip

Below is new registers dump, but I still can not get test pattern on my LVDS panel

reg0x00: 35h 38h 49h 53h 44h 20h 20h 20h - 01h 00h 85h 10h 00h 01h 00h 00h
reg0x10: 26h 00h 1Dh 00h 00h 00h 00h 00h - 7Ah 00h 03h 00h 00h 00h 00h 00h
reg0x20: 00h 04h 00h 00h 58h 02h 00h 00h - 21h 00h 00h 00h 14h 00h 00h 00h
reg0x30: 05h 00h 00h 00h 96h 00h 14h 00h - 96h 00h 0Ah 00h 10h 00h 00h 00h
reg0x40: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x50: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x60: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x70: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x80: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x90: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xA0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xB0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xC0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xD0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xE0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xF0: 00h 00h 00h 00h 40h 00h 00h 80h - 00h 00h 00h 00h 00h 00h 00h 00h

Does that mean I do not have a proper MIPI DSI clock configuration? Is there any SN65DSI83 status register to track the problem cause, such as input clock?

Thanks,

Dennis

BTW, most of time, I can got reg#0xE5 = 0x0. Does that mean I have DSI clock already?

Hi,

I would recommend using the reference clock instead DSI clk if possible as the reference clock will provide better jitter performance than the DSI CLK.

Looking at the panel spec, it looks there is a mis-match between the input to the DSI Tuner and the spec. 

The typical DCLK frequency is 51.2MHz

Horizontal and vertical front and back porch need to follow the panel spec 

The video format is format 2, not format 1

Thanks

David

Hi, David,

I was told the reference clock pin pulls to GND, so, I can not use REFCLK.

The reason to use 49.5M, is because soc can only output below sets of pclk, and 49.5 is closest to 51.2M

/* 65 MHz pixel clock */
/* 108, 40.5 MHz pixel clock */
/* 40 MHz pixel clock */
/* 31.5, 25.2 MHz pixel clock */
/* 101 MHz pixel clock */
/* 148.5, 75.25, 27, 49.5 MHz pixel clock */
/* 28.8 MHz pixel clock */
/* 28.3 MHz pixel clock */
/* 135, 67.5 MHz pixel clock */
/* 78.8 MHz pixel clock */

I did test format2, and problem keeps same.

Regards,

Dennis

Dennis

Did you also change the front and vertical blanking time programming value to match with the panel requirement?

Are you also following the DSI83 power up sequence? For scope waveform of the power up sequence, please refer to this e2e link, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85.

Thanks
David

Yes, I just change to below:, and problem keeps same:

#define PIXEL_CLOCK_KHZ 49500
#define H_PIXELS_LENGTH 1024
#define H_FRONT_PORCH 160
#define H_BACK_PORCH 160
#define H_SYNC_LENGTH 1
#define V_LINES_LENGTH 600
#define V_FRONT_PORCH 12
#define V_BACK_PORCH 23
#define V_SYNC_LENGTH 1

here is register dump:

reg0x00: 35h 38h 49h 53h 44h 20h 20h 20h - 01h 00h 83h 10h 00h 01h 00h 00h
reg0x10: 26h 00h 1Dh 00h 00h 00h 00h 00h - 78h 00h 03h 00h 00h 00h 00h 00h
reg0x20: 00h 04h 00h 00h 58h 02h 00h 00h - 20h 00h 00h 00h 01h 00h 00h 00h
reg0x30: 01h 00h 00h 00h A0h 00h 17h 00h - A0h 00h 0Ch 00h 10h 00h 00h 00h
reg0x40: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x50: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x60: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x70: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x80: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x90: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xA0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xB0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xC0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xD0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xE0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xF0: 00h 00h 00h 00h 40h 00h 00h 80h - 00h 00h 00h 00h 00h 00h 00h 00h

I do not have an oscilloscope to show my scope waveform of the power up sequence, but i follow a sequence of below as datasheet:

Hi, David,

I found a scope to probe LVDS output from the DSI83:

LVDS_CLK_N/P: always ~1V, no GOOD!!

OUT0_N/P, OUT2_N/P: always ~1V, no GOOD!!

I changed to use another display timing and initialization, which were proved to work good on previous old board with same DSI83 chip. And, I get same signal as above from scope. Below is registers dump.
reg0x00: 35h 38h 49h 53h 44h 20h 20h 20h - 01h 00h 85h 10h 00h 01h 00h 00h
reg0x10: 26h CCh 2Eh 00h 00h 00h 00h 00h - 78h 05h 03h 00h 00h 00h 00h 00h
reg0x20: 00h 05h 00h 00h 20h 03h 00h 00h - 40h 00h 00h 00h 28h 00h 00h 00h
reg0x30: 14h 00h 00h 00h 37h 00h 23h 00h - 4Bh 00h 3Ah 00h 00h 00h 00h 00h
reg0x40: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x50: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x60: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x70: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x80: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0x90: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xA0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xB0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xC0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xD0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xE0: 00h 00h 00h 00h 00h 00h 00h 00h - 00h 00h 00h 00h 00h 00h 00h 00h
reg0xF0: 00h 00h 00h 00h 40h 00h 00h 80h - 00h 00h 00h 00h 00h 00h 00h 00h

BTW, register0xE5=0x0, does it mean anything?

Thanks,

Dennis

Dennis

Can you also probe the DSI input clock and send me the schematic/layout?

Thanks

David

That is problem that I do not have schematics for DSI input, and I cannot probe that. But, 0xE5 did not report any DSI error, and I did SOFT_RESET, and no PLL_UNLOCK error from 0xE5.

Dennis

Thanks for the update, I am glad you are able to find the root cause and solve this issue.

David