TS3USBCA4: FLIP selection Pin swapping issue

you mean when Flip is low, SBU1/SBU2 flip and Flip is high, SBU1/SBU2 is normal?

Can you send shematic?

Regards

brian

Hi Brian, 

Yes, you are right. 

When Logic Low --> SBU1 and SBU2 are flipped and When Logic High SBU1 and SBU2 are normal. Here is the circuit attached. Let me know if the logic levels mentioned in the datasheet is proper or not ?

Ok, Let me check with design and give you feedback.

Regards

brian

Hi Brian , do u have any update on this regard?

sorry, lots of people out this week due to holiday.

Regards

brian

Hi Brain, I have not heard from you .its been a while, do you have the resolution?

sorry for late.

 The validation data  shows it working as expected, but I will check again on our EVM by this week.

Regards

Brian

Hi Brain,

I Am Looking forward to this data. I cross verified this with my boards as well, yet its swapped if i follow as per datasheet

I confirmed on our board datasheet sheet is correct.

Maybe you need to remove PD on SLE pin?

Regards

Brian

Hi Brian,

Do you mean SEL0 and SEL1 pulldown resistor removal?

How does that resolve the issue?

Sorry, I was thinking something goes high.

How did you do the test? Did you confirm in layout , routing is correct?

Regards

brian

Hi Brian,

I Have Rigged up the circuit in the General Purpose PCB and verified it by providing 3.3 V on Pin 11 and 0V to Pin 10 the Flip pin functionality is as same in the Datasheet Truth Table. When the Flip pin is 0 pin 7 is 3.3V and Flip Pin is 3.3 then the Pin 7 is 0V. 

But when testing with my circuit the P and N are swapped when Flip 0. I have attached the full circuit for your review. if could see any mistakes in it.

I have checked the signal continuity with the DMM schematic and routing seems to be no signal swapping. Can you help what could be the suspect.

This is source application?

Can you get more schematic ? I wan to see full range of AUXP_P2 and AUXN_P2?

Regards

brian

Hi Brian,

Yes, am using this for the DP sink /Source application. this P and N are swapped between the input and output pins of the MUX Switch only while I'm debugging I just probed the whole path to see where the signal is swapped. Only at the pin 11/10 and 7 /8 of the mux switch has the signal swap rest of the path is fine.

This is the full signal flow schematic, attached the signal block diagram as well for better understanding.

I still think something is wrong other than TS3USBCA410, need to check scematic or layout again.

regards

brian

any update?