Hi,
We are looking to drive a dual pixel LVDS LCD from a single pixel 24 Bit parallel interface, and I'm having trouble understanding the DS90C387 spec sheet.
The LCD has dual port LVDS input with 74.25 Mhz clock JEIDA, (LVDS dual pixel balanced -Odd 0 -3 data plus clock and Even 0-3 plus clock) DE mode only. We are looking to drive it with a STM32F743 24 bit RGB parallel output via the DS90C387.
in "single input pixel-to-dual pixel output" mode, is it possible to clock in 2x 24 bit pixels (odd and even pixels @ double clock rate) to have the output to the LCD send normal clock rate with the 2 pixels separated on the LVDS ports (odd and even pixels)?
Or does "single input pixel-to-dual pixel output" split the 24 bit pixel data to 2 x 12 bit pixels @ normal clock rate, but lower colour depth?
Or is there a more appropriate Dual LVDS IC?
If anyone can clarify the operation for me, would be greatly appreciated.
