DS90UH949A-Q1: I2C Watchdog and BCC Watchdog questions

Hey Alex,

There is an apps note for I2C - it explains clock stretching, etc. but not for watchdog feature.

https://www.ti.com/lit/an/snla131a/snla131a.pdf?ts=1670270259362

Alex Reid1 said:

• Are there any additional app notes that describe the I2C bus timer and BCC watchdog in more detail?
• For “I2C Bus Timer” (Reg 0x05 on 949, 0x06 on 940), I’m wondering which “side” of the serdes links this effects.
  • So for example, if this is enabled on 940, will SDA stuck-low on the deserializer side of link cause “driving 9 clocks on SCL” to occur on the serializer side of link? 
  • Is there a register bit that gets set in such an event?

It will effect the transactions originated on the side this feature is programmed at. Example, if the host controller is on Ser side and you program this watchdog control and timer on Ser side, it's the responsibly of the Ser to provide an ACK signal back to the host controller which means the Ser will clock stretch until the transaction goes across the link and is replicated and gets a true ACK from the slave and sent back thru the backchannel. Throughout all that period Ser holds the bus low. 

Alex Reid1 said:

For BCC Watchdog Timer:  How is a “Control channel operation” defined?  In context of I2C, is this everything from start-bit to stop-bit?  Wondering if there’s any chance a clock-stretching responder device could cause this to trip, and if so, what happens on bus.

• Is there a register bit that gets set in such an event?

The BCC watchdog basically determines how long it's going to wait before it releases the bus back to the SoC. It's not from start bit to stop bit, it's only during clock stretching. Basically when there is an active BCC event.

In Summary:

I2C Bus timer:

• Only works when the serializer or deserializer is acting as the proxy I2C master, and it detects lock-up conditions on the local I2C bus. 
• If the I2C bus watchdog timer is enabled, the device will detect one of two conditions. 
  • If SDA and SCL are both inactive (high) for greater than 1second, the proxy I2C master will assume the bus is free. 
  • If instead, SDA is low with SCL high, but there is no activity on the bus for more than 1 second, the I2C master will attempt to generate pulses on the SCL signal.  This essentially tries to free up the bus if an I2C slave is incorrectly driving the bus following a transaction.  

BCC Watchdog Timer:

• It prevents a lock-up condition on the control channel when no response is available from the remote/remote-slave device.  
• The BCC Watchdog timer is active for both I2C master and slave operation, but only when the device is actively holding SCL low.
• An example of when this might happen is if link becomes lost before or during a control channel access.  In this case, no response will arrive from the remote serializer or deserializer.  If no response is seen within the timer window, the serializer/deserializer will release the SCL and indicate a not acknowledge on the I2C bus.  

Regards,
Fadi A.