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SN65DSI84: LVDS pattern generator output ok - no MIPI data displayed

Lo2
Expert 1935 points
Part Number: SN65DSI84


Hello,

we use a SN65DSI84 to convert from MIPI to LVDS. We have a working setup for a 10.1" display using single channel LVDS.

Now we attached a 21.5" 1080p panel using dual channel LVDS.

For the configuration we use the https://www.ti.com/tool/DSI-TUNER (this links to the old version 2.0 but we use 2.1 that can be found in this forum. The installer attempts to download a JRE from www.sun.com which fails, so install a recent JRE first).

MIPI is 4 lane, non burst video mode, event sync, format RGB888.

Panel timing (dual channel LVDS):

clock = 148500, /* kHz */
hdisplay = 1920,
hsync_start = 1920 + 2 * (60),
hsync_end = 1920 + 2 * (60 + 32),
htotal = 1920 + 2 * (60 + 32 + 48), /* 2200 */
vdisplay = 1080,
vsync_start = 1080 + 33,
vsync_end = 1080 + 33 + 4,
vtotal = 1080 + 33 + 4 + 8, /* 1125 */

datasheet:

After initialization via I2C we can enable the built-in pattern generator by setting 0x3c to 0x10. The LVDS the shows the bar pattern, the LVDS data and clock are correct. The note on the datasheet says "DE mode only",  apparently DE pulses are generated correctly. So I assume that the path SN65DSI84 -> LVDS panel is ok.

Since we have no external crystal, the LVDS clock (74.25MHz) is derived from  the MIPI clock (445.5MHz), that seems to work too.

Also the register 0x5e remains 0x00, I assume that:

- PLL is locked properly

- there are no MIPI protocol errors (CRC, ECC, protocol related bits are 0)

- there are no synchronization errors, i.e. H-sync and V-sync are detected properly

Is that correct?

Here is the annotated initialization:

# reset registers
i2cset -y 1 0x2c 0x09 0x01
sleep 0.05

# disable pll
i2cset -y 1 0x2c 0x0d 0x00
sleep 0.05

# lvds range 74.25 MHz - lvds pixel clock from mipi A
i2cset -y 1 0x2c 0x0a 0x05
# div refclk by 6
i2cset -y 1 0x2c 0x0b 0x28
# mipi = 4 lanes
i2cset -y 1 0x2c 0x10 0x26
# no equalization
i2cset -y 1 0x2c 0x11 0x0C
# dsi clock range (445.5MHz)
i2cset -y 1 0x2c 0x12 0x59
i2cset -y 1 0x2c 0x13 0x00

# lvds - dual channel - 24bbp - format1
i2cset -y 1 0x2c 0x18 0x6c
i2cset -y 1 0x2c 0x19 0x00
i2cset -y 1 0x2c 0x1a 0x03
i2cset -y 1 0x2c 0x1b 0x00

# timings
i2cset -y 1 0x2c 0x20 0xc0
i2cset -y 1 0x2c 0x21 0x03
i2cset -y 1 0x2c 0x22 0x00
i2cset -y 1 0x2c 0x23 0x00
i2cset -y 1 0x2c 0x24 0x38
i2cset -y 1 0x2c 0x25 0x04
i2cset -y 1 0x2c 0x26 0x00
i2cset -y 1 0x2c 0x27 0x00
i2cset -y 1 0x2c 0x28 0x21
i2cset -y 1 0x2c 0x29 0x00
i2cset -y 1 0x2c 0x2a 0x00
i2cset -y 1 0x2c 0x2b 0x00
i2cset -y 1 0x2c 0x2c 0x20
i2cset -y 1 0x2c 0x2d 0x00
i2cset -y 1 0x2c 0x2e 0x00
i2cset -y 1 0x2c 0x2f 0x00
i2cset -y 1 0x2c 0x30 0x04
i2cset -y 1 0x2c 0x31 0x00
i2cset -y 1 0x2c 0x32 0x00
i2cset -y 1 0x2c 0x33 0x00
i2cset -y 1 0x2c 0x34 0x30
i2cset -y 1 0x2c 0x35 0x00
i2cset -y 1 0x2c 0x36 0x08
i2cset -y 1 0x2c 0x37 0x00
i2cset -y 1 0x2c 0x38 0x3c
i2cset -y 1 0x2c 0x39 0x00
i2cset -y 1 0x2c 0x3a 0x21
i2cset -y 1 0x2c 0x3b 0x00
i2cset -y 1 0x2c 0x3c 0x00
i2cset -y 1 0x2c 0x3d 0x00
i2cset -y 1 0x2c 0x3e 0x00

# clear errors
i2cset -y 1 0x2c 0xe5 0xff
sleep 0.05

# enable pll
i2cset -y 1 0x2c 0x0d 0x01
sleep 0.05

# reset
i2cset -y 1 0x2c 0x09 0x00
sleep 0.05

# clear errors
i2cset -y 1 0x2c 0xe5 0xff

Are there any mistakes in the initialization?

Does the SN65DSI84 generate DE pulses from H/V sync MIPI information?

How can I debug further?

Br,

Lo2

  • 0
    TI__Genius 13310 points

    Hello Lo2,

    From reading your post I see that you have the color bar pattern working correctly. A correctly working color bar pattern shows that the device's LVDS side of the link is working appropriately. This points to the MIPI DSI side of the link that you will need to check.

    Could you please use a scope to verify that the initialization sequence looks alright? I would like to see how the EN, DSI_DATA, DSI_CLK and I2C pin look during the initialization sequence.

    An example is shown here: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85. 

    Thanks,
    Zach

  • 0 in reply to Zach Dryer
    Expert 1935 points

    Hi Zach,

    this is difficult as both chips are BGA versions, so I have no direct access to all the pins. Would SDA/SCL be sufficient? I could solder wires to the I2C pull ups. EN is a direct connection.

    Here is the whole init (including the GPIO controlling the enable pin). I highlighted the delays:

    echo   0 > /sys/class/gpio/gpio478/value
    sleep 0.05
    echo   1 > /sys/class/gpio/gpio478/value
    sleep 0.05

    # reset registers
    i2cset -y 1 0x2c 0x09 0x01
    sleep 0.05

    # disable pll
    i2cset -y 1 0x2c 0x0d 0x00
    sleep 0.05

    # lvds range 74.25 MHz - lvds pixel clock from mipi A
    i2cset -y 1 0x2c 0x0a 0x05
    # div refclk by 6
    i2cset -y 1 0x2c 0x0b 0x28
    # mipi = 4 lanes
    i2cset -y 1 0x2c 0x10 0x26
    # no equalization
    i2cset -y 1 0x2c 0x11 0x0C
    # dsi clock range (445.5MHz)
    i2cset -y 1 0x2c 0x12 0x59
    i2cset -y 1 0x2c 0x13 0x00

    # lvds - dual channel - 24bbp - format1
    i2cset -y 1 0x2c 0x18 0x6c
    i2cset -y 1 0x2c 0x19 0x00
    i2cset -y 1 0x2c 0x1a 0x03
    i2cset -y 1 0x2c 0x1b 0x00

    # timings
    i2cset -y 1 0x2c 0x20 0xc0
    i2cset -y 1 0x2c 0x21 0x03
    i2cset -y 1 0x2c 0x22 0x00
    i2cset -y 1 0x2c 0x23 0x00
    i2cset -y 1 0x2c 0x24 0x38
    i2cset -y 1 0x2c 0x25 0x04
    i2cset -y 1 0x2c 0x26 0x00
    i2cset -y 1 0x2c 0x27 0x00
    i2cset -y 1 0x2c 0x28 0x21
    i2cset -y 1 0x2c 0x29 0x00
    i2cset -y 1 0x2c 0x2a 0x00
    i2cset -y 1 0x2c 0x2b 0x00
    i2cset -y 1 0x2c 0x2c 0x20
    i2cset -y 1 0x2c 0x2d 0x00
    i2cset -y 1 0x2c 0x2e 0x00
    i2cset -y 1 0x2c 0x2f 0x00
    i2cset -y 1 0x2c 0x30 0x04
    i2cset -y 1 0x2c 0x31 0x00
    i2cset -y 1 0x2c 0x32 0x00
    i2cset -y 1 0x2c 0x33 0x00
    i2cset -y 1 0x2c 0x34 0x30
    i2cset -y 1 0x2c 0x35 0x00
    i2cset -y 1 0x2c 0x36 0x08
    i2cset -y 1 0x2c 0x37 0x00
    i2cset -y 1 0x2c 0x38 0x3c
    i2cset -y 1 0x2c 0x39 0x00
    i2cset -y 1 0x2c 0x3a 0x21
    i2cset -y 1 0x2c 0x3b 0x00
    i2cset -y 1 0x2c 0x3c 0x00
    i2cset -y 1 0x2c 0x3d 0x00
    i2cset -y 1 0x2c 0x3e 0x00

    # clear errors
    i2cset -y 1 0x2c 0xe5 0xff
    sleep 0.05

    # enable pll
    i2cset -y 1 0x2c 0x0d 0x01
    sleep 0.05

    # reset
    i2cset -y 1 0x2c 0x09 0x00
    sleep 0.05

    # clear errors
    i2cset -y 1 0x2c 0xe5 0xff

    Br,

    Lo2

  • 0 in reply to Lo2
    TI__Genius 13310 points

    Hello Lo2,

    I am not looking for the timing delays between your I2C bus commands.

    I want to help verify when you enable the device if your clock and data lanes are in the right states per the initialization sequence in the datasheet (see Section 7.4.3 Initialization Sequence). This is not evident by the sleep commands that you are showing me above.

    Thanks,

    Zach

  • 0 in reply to Zach Dryer
    Expert 1935 points

    Hi Zach,

    we have video output now, we figured out that the registers 0x20/0x21 must be set to 1920 for normal operation but to 960 when the generator is active. When set to 1920 the output is shown on the panel.

    Running fb-test shows that we do have a vertical offset of 12 lines, so apparently out vertical sync needs some adjustment.

    Which mode is preferred? Should we use MIPI sync pulse mode or MIPI event mode?

    Br,

    Lo2

  • 0 in reply to Lo2
    TI__Guru**** 181261 points

    Lo2

    The SN65DSI84 supports burst video mode and non-burst video mode with sync events or with sync pulses packet transmission.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Expert 1935 points

    Hi David,

    thanks for your answer.

    Then I assume that the v-sync issue is related to the output (LVDS settings) then?

    Here are some pictures:

    upper left corner:

    These leading empty rows (about 12 lines) should not be there. H-sync looks good, no tearing/jitter.

    Lower left corner:

    Some lines are missing here, the diagonal should go to the corner.

    Best regards,

    Lo2

  • +1 in reply to Lo2
    TI__Guru**** 181261 points

    Hi, Lo2

    Please refer to this e2e FAQ link, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/918890/faq-sn65dsi84-how-to-configure-the-sn65dsi84-and-sn65dsi85-for-single-channel-dsi-to-dual-channel-lvds. It looks like your pixel frequency calculation, and horizontal blanking values are not being programmed correctly.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Expert 1935 points

    Hi David,

    Hi Zach,

    thanks for your support. We found the issues: the MIPI timings for Vsync/Hsync set in the kernel were not applied by the driver, the MIPI interface ignored the sync settings. So the MIPI timing was wrong (Vsync way too short).

    It now works just fine, thanks!

    Br,

    Lo2