DP83TG720R-Q1: The output RMS jitter of the Gigabit Ethernet MDI is out of range

Hi Yin,

Can you please share me the following conditions used for testing?

1. Which test mode is used?
2. Is the jitter measured in Master mode or Slave mode?
3. Can you please share the images of the setup?
4. Can you please share if you have images of the measurement (i.e., jitter histograms etc)

--
Regards,
Gokul.

1、Test Mode 1

2、Slave

3、

4、Probably not

• Sorry, I have the wrong number

• 1、TEST Mode 2

Hi Yin,

Can you please share the following?

1. Scope capture of the MDI signals
2. Peak-peak jitter measurement value
3. Histogram of the jitter

--
Regards,
Gokul.

Hi Yin,

Can you please share the schematic of your design?

What is the source of the input clock (on XI,XO) in your design? Are you using an external clock or using an oscillator?

--
Regards,
Gokul.

I can not share the schematic.

 Using an oscillator, 25Mhz

Hi Yin,

Higher jitter can be caused due to many of the following reasons like setup, probe and scope inaccuracy, coupling of some other signals to MDI, supply and ground noise etc.

I see that measured value is very marginally failing which means we are close, but need to look into what is making this bad.

Can you please measure TX_TCLK during this test mode? This should be available on CLKOUT by default in testmode2. Else, I can let you know the register configuration.

Can you also measure the jitter CLKOUT_25MHz (25MHz clock) after forcing the device into RESET (i.e., holding RESET_N low always)? This should give us an indication if the problem is inherently with crystal oscillator jitter.

--
Regards,
Gokul.