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DS90UB948-Q1: LOCK signal is unstable

zhijian Mao
Prodigy 130 points
Part Number: DS90UB948-Q1


Hi，TI

In bring up,FPD-LINK has the following problems.Please refer to the simple system block.

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/138/3146.block.PNG

1. At initial power-up, the 948's lock signal was unstable. When the PDB is high, the LOCK is stable high after 1s.

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/138/5226.tek00012.png

2. Some control signals are configured through the local GPIOs of the 948, but occasional failures occur.

Seen by a logic analyzer,when LOCK is low, the SOC is configuring the registers on the 948 side through the 941.

Does this cause the above problem?

For this case，please help answer the following questions

1. What is the reason for the LOCK instability at initial power-up

2. Will the EVM board LOCK also appear unstable?

3. When LOCK is low, can I initially configure the 948?Can I I2C configure a 948-side slave device?

4. Refer to Table 2. Output State Table, Reg 0x02 [7] and Reg 0x02 [4] need to be configured to 1 when 948 is initialized?

5. What value is usually configured for Reg 0x02 initialization, and is bit5 only used during BIST?

Thanks

  • 0
    TI__Mastermind 22946 points

    Hi Zhijian,

    Thank you for the question. 

    1. Expectations about intermittent lock is that system should not have marginal lock given a system conforms to channel specification, device limits/specifications, etc. There are many causes about no lock as below. 

    • Strap issue / register issue (incorrect strap or register configuration for target FPD rate/config)
      Deserializer MODE SEL0/1 settings must be configured to target rate/config. SER straps can be overridden via config script
    • Hardware/cable issue (faulty cable/CMC/connector, routing issues, incorrect port, etc

    2. If Lock LED on EVM board is on, it indicates that strap are configurated to target. EVM doesn't make to change any configuration.

    3. If it is unlocked, it means there is not linked between serializer and deserializer.

    4-5. Could you clarify table 2? It doesn't look the Reg 0x02 table (GENERAL_CONFIGURATION_0) in datasheet.

    Please make sure the strap and configuration are correct. If it is matched, we need to check specification like timing or channel. Also, it would be appreciated if you could provide better quality for reference block diagram or logic analyzer result at next time.

    Regards,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 130 points

    1. DES   MODE_SEL0=[#5] , MODE_SEL1=[#2]      SER  MODE_SEL0=[#3] , MODE_SEL1=[#2] 

    2. The LOCK signal of other projects of our company will also be unstable at the beginning of power-up,

    Since there is an MCU on the 948 side, there will be no problem of configuring the 948 failure due to LOCK failure.

    3. The prerequisite for a link between SER and DSE requires both SER and DSE to have PDB enabled？

    The timing of the PED of the SER and the PDB of the DSE has not been measured. I'll confirm later

    When LOCK is in a thi-state , the LOCK signal should also be unstable?

    3. table2

    Is there a way to test Serial Input's Static and Active state hardware?

    According to table2, the input state should be satisfied first, and the LOCK is high.
    However 0x02 registers need to be configured from the SER side, when LOCK is low, the ser can be configured with DSE？

    Detailed test results will be given to you later.

  • 0 in reply to zhijian Mao
    TI__Mastermind 22946 points

    Hi Zhijian,

    zhijian Mao said:

    However 0x02 registers need to be configured from the SER side, when LOCK is low, the ser can be configured with DSE？

    Are you asking DES 0x02 register is able to write from SER side even LOCK is low?

    zhijian Mao said:

    When LOCK is in a thi-state , the LOCK signal should also be unstable?

    Yes. it would be unstable because LOCK signal in toggling during tri-state. I don't think there isn't a way to check the input status (static or active ) on hardware, but I will let you know after discussion with team. In meantime, could you clarify when 941 is started to send the video? Also, you need to check the cabling mode are matched between SER and DES since it looks like you set coax mode in SER and STP mode in DES.

    Regards,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 130 points

    thank you

    Are you asking DES 0x02 register is able to write from SER side even LOCK is low?

    yes, because there is no configuration 0X02 before, the lock signal should be low.

    DES   MODE_SEL0=[#5] , MODE_SEL1=[#2]      SER  MODE_SEL0=[#3] , MODE_SEL1=[#2] 

    Compare MODE_SEL tables, both are coaxial mode.

     In meantime, could you clarify when 941 is started to send the video?

    I don't know about this, I need to communicate with software colleagues

  • 0 in reply to zhijian Mao
    TI__Mastermind 22946 points

    Hi Zhijian,

    You can write Deserializer 0x02 register from SER side even LOCK is low, but note that it is not comminuted with Deserializer as you know.

    Could you clarify where the table is from? In the datasheet on our website, MODE_SEL2 #2 for 948 is STP mode as below. Please refer to datasheets from DS90UB941AS-Q1 & DS90UB948-Q1 and then check the modes and straps are matched.

    Regards,
    Josh
  • 0 in reply to Josh Baik
    Prodigy 130 points

    About MODE_SEL,since my 948 datasheet is an old version.According to the voltage value, it has been confirmed that the setting is fine, and it is all coax mode.

    Even if LOCK is low, as long as the PDB of 948 is high, all registers of the 948 can be configured on the 941 side.

    Is this understanding correct? 

    But when LOCK is low, the slave devices on the 948 side can configure the I2C register through the 941？

  • 0 in reply to zhijian Mao
    TI__Mastermind 22946 points

    Hi Zhijian,

    To clarify, if LOCK is low, it can't be configured to 948 or slave device.

    If LOCK status is unstable, it indicates because of DSI data from serializer side. Please double check DSI signal, DSI PCLK, stability, jitter, etc.

    Regards,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 130 points

    Hi, Josh

    Josh Baik said:
    To clarify, if LOCK is low, it can't be configured to 948 or slave device.

    Thanks, I already got it

    Josh Baik said:
    Please double check DSI signal, DSI PCLK, stability, jitter, etc.

    But the eye pattern of the coax mode has not been tested before, is it correct for the hardware circuit to draw it this way？

  • 0 in reply to zhijian Mao
    TI__Mastermind 22946 points

    Hi Zhijian,

    I mean you should check at serializer side, not deserializer side. Please refer to DSI clock timing, DSI data-clock timing on AC electrical characteristics in 941 datasheet and double check that the PCLK is also covered to the desired data rate.

    Regards,

    Josh

  • 0 in reply to Josh Baik
    Prodigy 130 points

    Hi, Josh

    Okay, got it, thanks

    Josh Baik said:
    To clarify, if LOCK is low, it can't be configured to 948 or slave device.

    sorry, follow your reply, If the 0x02 register of the 948 cannot be configured, according to the output status table of the 948, the LCOK can only be high after the configuration is 0x02

    Sorry, I didn't figure it out.Please help confirm that I will also conduct the actual test

  • 0 in reply to zhijian Mao
    TI__Mastermind 22946 points

    Hi Zhijian,

    It is not correct. Let's clarify the concept about LOCK at first. LOCK is the link status between serializer and deserializer and it would be high when mode selections are matched, and it is not depending on others on Output State Table you shared. 

    The default 0x02 [7] and 0x02 [4] are high. Thus, PASS, Data GPIO, and D[7:0]/CLK[2:1] would be valid when Serial Input is active, PDB is high, and LOCK is high that is when mode selections are matched between serializer and deserializer.

    Since your LOCK status is unstable or with delayed time, we need to consider the serializer input. As I told before, if the lock is unstable make sure clock/data/sync is stable and no jitter at serializer input and the correct polarity is connected to the deserializer. If the LOCK is only low sometimes it can be caused by power supply noise or quality of input PCLK or the serial data eye. That is why I asked you DSI data at serializer input.

    Regards,

    Josh