TCAN4550: Temperature Affects TCAN5440 Communication

Hi NAN,

This temperature related error does sound like it is caused by the clock circuit and I will try to explain to you how the device works and answer your questions.

The TCAN4550 was designed to support two different types of clocks and it will automatically detect which type of clock is used for fast startup times.  The two types of clock it can use is either a Crystal Oscillator or a single-ended clock with a waveform swinging between 0V and VIO which is either 3.3V or 5V.

When a Crystal Oscillator is used, the TCAN4550 will source current out of the OSC1 pin to support the oscillation created by the inductance of the crystal and the capacitance of the load capacitors and board parasitic capacitance.  The TCAN4550 has a peak detector and automatic gain control circuit that monitors the oscillation voltage on the OSC1 pin and adjusts the amount of current sourced to the crystal to maintain an ideal oscillation amplitude of 1Vpp.  If the peak-to-peak oscillation voltage exceeds 1Vpp, then the TCAN4550 will source the minimum level of current to the crystal.

The OSC2 pin is the input of the crystal oscillator to the TCAN4550 and it will take this oscillation waveform created by the crystal and convert it into the internal working clock used by the TCAN4550. 

Also included in on the OSC2 pin is a digital comparator that is used to detect a "grounded" pin which is the method used to enable the single-ended clock mode.  The voltage threshold of this comparator is used to determine whether the pin is "grounded"  and is set to approximately 100mV.  Due to device-to-device variation and worst case semiconductor process variation, the actual threshold for this comparator will vary slightly on different devices, but it will be somewhere between 90mV and 150mV as a min/max spec for this parameter.

A 1uA current source is used to supply a small current to the OSC2  pin and when the device starts up, if the pin is grounded, this current will flow to GND and the OSC2 pin voltage will be less than 100mV causing the device to power up in single-ended clock mode.  In this mode the external single-ended clock is to be input to the TCAN4550 on the OSC1 pin.  However, because the OSC1 pin is also used as the output of the trans impedance amplifier used in the Crystal mode, the crystal amplifier must be disabled in single-ended mode so that it can become an input pin in single-ended mode.

When the OSC2 pin is NOT grounded for use with a crystal, the small 1uA current will not have a good path to ground and cause the OSC2 pin to be above the 100mV single-ended detection comparator threshold.  This will cause the TCAN4550 to boot up with the trans impedance amplifier enabled and the device will start to source current out of the OSC1 pin to the crystal.  Initially the TCAN4550 will source the maximum amount of current to the crystal to charge the load capacitance and start the oscillation.  Once this oscillation starts, the automatic gain control circuit will start to reduce this current to simply replace the current lost through the parasitic resistance in the circuit.

When the crystal is oscillating, the voltage on the OSC2 pin "should" be greater than 100mV at all times with a 1Vpp amplitude and a common mode voltage typically around 600mV to 700mV.   The exact voltage levels are created by RLC parameters and the voltage dividers created from the components in the circuit (load capacitors, dampening resistors, and motional inductance, capacitance, and resistance of the crystal), etc. 

The oscillation voltage that is created is proportional to the mechanical vibration created by the crystal and increasing the current flowing through the crystal will increase the voltage amplitude.

If the components in this circuit are not optimized, the oscillation voltage levels may cause the OSC2 pin voltage to drop below the single-ended detection comparator's 100mV (typ) threshold and cause the TCAN4550 to switch to single-ended clock mode. The automatic gain control circuit has a "minimum" amount of current that it must source, and if the components in the circuit are not properly selected, this minimum current may still be more current that is needed and the oscillation amplitude may exceed the ideal 1Vpp value.  The common mode voltage of the oscillation may not change much and still be centered about 600mV to 700mV, but a higher peak-to-peak voltage will cause the Highest "peak" and Lowest "peak" voltage levels of the waveform to increase and decrease respectively.  If lowest "peak" voltage of the oscillation waveform becomes too low, this can cause the single-ended detection voltage to think the OSC2 pin is "grounded".

When this occurs, the device will disable the trans impedance amplifier sourcing current to the crystal on the OSC1 pin and expect a single ended clock to be input on this pin instead.  However, because there is not a single-ended clock when using a crystal, the TCAN4550 will not have a valid clock and the communication will be disabled.  But, without current flowing to the crystal, the oscillation amplitude will decay and the OSC2 pin voltage will increase which will allow the device to switch back to crystal mode.  This process of switching between the two clock modes may repeat itself with a non-optimized circuit.

In addition to the capacitance from the load capacitors, the PCB and TCAN4550 parasitic pin capacitance must be accounted for as part of the total load capacitance used in this circuit.  This parasitic capacitance is not as stable across temperature like the higher quality capacitors used as load capacitors.  When the temperature increases, the amount of parasitic capacitance seen by the circuit changes and this impacts the oscillation waveform because this is changing the capacitance in the circuit.  This is why you are able to create the communication problem by increasing the temperature.

Therefore, to answer your first question, we need to optimize the circuit to prevent the lowest "peak" voltage level of the OSC2 waveform from dropping below 150mV across all temperature conditions.  We should also try to provide additional margin between the lowest peak voltage on the OSC2 pin above this threshold if possible to ensure plenty of margin to account for manufacturing tolerance of the crystal and capacitors, etc.  With some crystals, a full 200mV of margin may not be possible, but the recommendation is to optimize the circuit to create as much margin as possible to ensure stability.

Your second question is essentially how do we optimize this circuit and create this margin.  The high level answer is that we need to reduce the current flowing through the crystal so that the mechanical vibration and the peak-to-peak voltage created by this vibration is reduced.

Because the minimum amount of current sourced by the TCAN4550 through the OSC1 pin to the crystal is more than the crystal needs, the preferred method is to place a series resistor between the OSC1 pin and the crystal to dampen or restrict the amount of current flowing through the crystal.  Including a series resistor between the OSC2 pin and the crystal will not restrict the current flowing through the crystal and is essentially on the wrong side of the crystal.

If a series dampening resistor between OSC1 and the crystal is not possible, then the only other option is to change the total resistive load of the circuit by increasing the value of the load capacitors.  The potential drawback to increasing the capacitance is that this will also create a small frequency shift in the oscillation frequency.  The good news is that the CAN standard has enough tolerance in the specification that this shift should not be a problem from a communication perspective. 

We have seen that a 50 to 100 ohm series dampening resistor on OSC1 provides the same result as increasing the capacitors by 3-4pF each.  This is why it is the preferred method for optimizing the circuit because it allows the capacitance to be tuned for the ideal frequency.  The trade off with the resistor though is that it reduces the negative resistance and safety factor.

I hope this clarifies how the TCAN4550 operates and answers your questions.

More information can be found in this application note: https://www.ti.com/lit/pdf/slla549

Regards,

Jonathan