TCAN1145-Q1: delay between two register write/read operations

Hi Prahlad,

Firstly, where are you getting the 50 us delay from? Are you saying that you are not able to send commands with less than a 50 us delay? Have you check your SPI driver to see what the commands look like when you use a shorter delay. Often times SPI drives are not fast enough for extremely fast SPI transactions. So the SPI drivers of your processor often have to be optimized to reach faster speeds.

For the TCAN1145 the SPI write is all defined in figure 9-10:

From one SPI command to another there will be the nCS disable time which is a minimum of 50 ns. So you need a minimum of 50 ns between your nCS going high to end the command and then it going low again for your device to recognize another command. The rest of the parameters of the SPI write are in that figure. If you have any questions about them let me know.

Best,

Chris

Hello Chris,

SPI clock is 4 MHz, and 5 us delay works for two register write operations, but it does not work in case of Mutiple register write operation. If I increase delay to 50 us, TCAN registers are getting written successfully. I verify it by reading back all the registers.

Hi Yogini,

Thanks for clarifying here. 

I am not aware of any additional disable time required by TCAN1145 when a burst write is used. Based on my experience, only the specified 5us is needed - thought I have not tested a case with a 4MHz clock. I will test this on an internal setup to verify this is what we expect from the device. 

If your test setup is still available, would it be possible to share scope shots of the burst SPI writes you are using? I would like to use these to compare with my own setup to ensure we are recreating the same conditions.

Regards,
Eric Schott 

Hi Yogini,

I am not yet able to reproduce the issue you describe here. I am able to reliably use a burst write to the SW_ID registers and read back the data correctly. My setup uses a 4MHz SPI clock and the delay between frames is less than 50us (~25us currently, though it may take some effort to lower this further on my setup). I've included a scope shot of my results below for your reference. Please let me know if there are any discrepancies between this and your current setup. 

Regards,
Eric Schott 

Hi Eric, 

Here , I have tried with the single register write operation only. I do not have the setup with me currently. But I can share the sample code which I have used. Please share your email ID. I will share the zip file.

Hi Yogini,

You can find my email address in my bio by clicking on my E2E name. 

Are you able to contact anyone that has access to the burst write setup or test results that would be able to share scope shots of the failure?

Regards,
Eric Schott 

Hi Eric,

I have sent you the sample code on your email ID. Did you get a chance to look into it?

Hi Yogini,

I don't see any issues with the code you sent, though I am not familiar with the SPI driver that is being used here. I think the best way to debug this would be if you can share scope shots of your testing so that I can recreate the same conditions on my setup. Do you think this would be possible?

Regards,
Eric Schott 

hi Eric,

Currently, we have HW constraint, hence cannot get the scope images.

Actually, the shared code is correct, but if you the value of DELAY parameter, it is 50 us. Which means, the delay between two read or write operations is 50 us. If I reduce it, Read/write operation fails for some registers. 

is it possible for you to Run the shared code on your setup? 

Hi Yogini,

My setup is not running C code, so it would not be trivial to run this on my end. Without more insight on the SPI driver on the MCU in use here, there's not much I can do apart from check high-level flow and syntax. If it's at all possible to share any data regarding what signals appear on the TCAN1145 pins directly, it would be much easier for us to approach this from a hardware perspective.

Regards,
Eric Schott