DP83TG720R-Q1: RGMII timing related input and output capacitance differences

Jing Liang

Hello Expert,

I found the RGMII time requirement(input capacitance and output capacitance ) of Tx_D0/ Tx_D1/Rx_D2/Rx_D3 RGMII data line are different with others data line, my question is why differential TI design behavior on the port?

over 3 years ago

0 Evan Mayhew over 3 years ago

TI__Mastermind 25548 points

Hi Jing,

This is due to the internal architecture of the PHY.

Thank you,

Evan

0 Jing Liang over 3 years ago in reply to Evan Mayhew

Prodigy 160 points

Does this has been worst case considered in the IBIS model already?

0 Evan Mayhew over 3 years ago in reply to Jing Liang

TI__Mastermind 25548 points

Reviewing the IBIS simulations for the 720, they appear to characterize the best, worst, and nominal cases for each version of the silicon.

Thank you,

Evan

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DP83TG720R-Q1: RGMII timing related input and output capacitance differences