SN65DPHY440SS: Skew tolerance on input

Max Larin

Part Number: SN65DPHY440SS

Hello Team,

We are using the subject part in our design and facing difficulties to match the propagation delay from the source, being a CSI-2 image sensor, to the inputs of DPHY on our PCB.
The question is: what skew on data lines and clock DPHY440 can tolerate on input?
Our design is 4 lanes, 1.5Gbps.

Thanks and with best regards,
Max

over 2 years ago

0 Brian Zhou over 2 years ago

TI__Guru*** 146695 points

The internal dynamic de-skew feature is enabled in HS mode, and causes a 2 clock (4 UI)
delay of data while data traverses from DA to D.

Regards

Brian

0 Max Larin over 2 years ago in reply to Brian Zhou

Prodigy 10 points

Hi Brian,

Than you for your response and valuable information.

My question is about skew on input between different data lanes. We have PCB technology difficulties to match propagation delay on data lanes and need to know what the subject part can tolerate on input. Is it +/- 1/2 of UI? Or some other margin? How part will behave if skew is higher than expected?

Thanks and best regards,
Max

0 Brian Zhou over 2 years ago in reply to Max Larin

TI__Guru*** 146695 points

IT'S better to keep lengths to within 5 mils of each other.

Regards

Brian

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SN65DPHY440SS: Skew tolerance on input