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DS250DF230: CDR lock is not stable

Okutsu
Prodigy 240 points
Part Number: DS250DF230

Hi, TEAM.

Our customer has asked us about a DS250DF230 with unstable CDR locks.

The block diagram in the upper part of the image (Default) is the configuration used in the operation.

The Cross Point of DS250DF230 is enabled and routed below.
　CPU(LX2160A) --> DS250DF230 --> SFP28
　SFP28 --> DS250DF230 --> CPU(LX2160A)

The block diagram in the bottom row (TEST 01) is the configuration looped back for verification.

　The Cross Point of DS250DF230 is not switched, so the route is as follows.
　CPU(LX2160A) --> DS250DF230 --> CPU(LX2160A)
　SFP28 --> DS250DF230 --> SFP28

In the two configurations, the CDR lock of the input signal (RX1) from CPU(LX2160A) is not stable, so the configuration in TEST 01 in the bottom row is verified.

Using the GUI tool of "SigCon Architect
Data rate: 25.78125 Gbps
Calibration Clock Pin (CAL_CLK_IN) of DS250DF230 is 30.72 MHz.
Signal Detected of input signal (RX1) from CPU (LX2160A) is OK.
Input signal (RX1) from CPU (LX2160A) is CDR Locked/Unlocked.

25G_Retimer_setup_01.cfg25G_Retimer_setup_01.xlsx
The attached "25G_Retimer_setup_01.cfg" is the data saved from "SigCon Architect".
data saved from "SigCon Architect".
Setup and start of operation is only as follows.

　1 "Reset Device
　2 "Apply to All Channels
　3 Reset CDR All Channels

Sheet "test_01" in "25G_Retimer_setup_01.xlsx" is each screen on "SigCon Architect".
　test_01_01.bmp CDR Unlocked(Channel 1 blue box)
　test_01_01a.bmp CDR Locked(Channel 1 blue frame)
The CDR lock is not stable.

I would like to get advice on where to check and what settings to make in order to stabilize the CDR lock.

Best Regards,

  • 0
    TI__Mastermind 36043 points

    Hi,

    Am I correct in assuming that CDR lock on RX1 is not stable regardless of crosspoint configuration?

    About how much insertion loss is between the CPU and RX1?  Is any chance of over equalization?  What is the VOD of the signal sent by the CPU?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi, Thank you for replying.

    The question resulted in:

    ・Is that correct in assuming that CDR lock on RX1 is not stable regardless of crosspoint configuration?　⇒ Correct.

    ・About how much insertion loss is between the CPU and RX1?　⇒ About -4db at 12.5Ghz.

    ・ Is any chance of over equalization?　⇒ Maybe there is a possibility.

    ・What is the VOD of the signal sent by the CPU?　⇒ About 300mV.

    With additional information,
    The substrate material is Megtron 6. And the wire length is as shown in the figure.

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thanks for providing an update.  I have a couple of experiments to try and see how this impacts CDR lock stability.

    1) Is it possible to increase CPU VOD?  This seems a bit on the low side.  I would be curious to know if a CPU VOD somewhere in the 600 mVpp - 1000 mVpp range improves CDR lock stability.

    2) Enable adapt mode 2 and DFE.  This allows the device to adapt both CTLE and DFE.  DFE can help improve the signal eye.

    3) In the event that the CPU signal is being over-equalized, there are a couple of things we can try to address this.  One is to enable CTLE boost override and manually set CTLE.  From the screenshots you sent, it appears CTLE was 3.  I would try working down from 3 to see if the eye improves.  The DS250DF230 also has a CTLE bypass, which bypasses 3 of the 4 CTLE boost stages.  This can be enabled by setting ch_reg_0x2D[3:2]. = 2'b11.  Please see programming guide for additional details.

    Please try these experiments and observe CDR lock stability and retimer HEO/VEO for each.  I think the results of these experiments will help us identify the root cause of CDR lock instability.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi,

    Thank you for your suggestion.
    I'll wait for the customer's reaction.

    Thanks,

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thanks, please let me know when you hear back.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi,

    Our customer asked us about the condition before the experiment.

    They were observing the "Eye Monitor" with the "SigCon Architect" in the TEST 01 configuration.

    Observe "Eye Monitor" in loopback on the CPU side.
    　CPU(LX2160A) --> DS250DF230 --> CPU(LX2160A)

    Also, as a comparison check, observe the "Eye Monitor" for the loopback on the SFP28 side.
    　SFP28 --> DS250DF230 --> SFP28
    The SFP28 side is connected to the opposing device (fiber managed switch) via 25G Transceiver (25GBASE-SR).

    In the sheet "test_01A" of the attached25G_Retimer_setup_01A.xlsx
    Each screen on "SigCon Architect" is attached.
    (The two screens are [CH0] on the left and [CH1] on the right)

    Since the Cross Point of DS250DF230 is not switched, it is guessed as follows.
    [CH0] SFP28 Loop (SFP28 --> DS250DF230 Retimer --> SFP28)
    [CH1] CPU Loop (CPU --> DS250DF230 Retimer --> CPU)

    In addition, the setting and operation start are the same as "TEST_01", only the following.
    　1 "Reset Device"
    　2 "Apply to All Channels"
    　3 "Reset CDR All Channels"

    [CH0] The input signal on the SFP28 side is stable,
    The opposing device (fiber managed switch) side maintains the Link Up state.
    ・Signal Detected of input signal (RX0) from SFP28 is OK
    ・CDR Locked of input signal (RX0) from SFP28 is stable

    From line 197 of the sheet "test_01A" in the attached "25G_Retimer_setup_01A.xlsx" is the "Eye Monitor" screen.
    Compared to the state of the input signal (RX0) from [CH0] SFP28, the voltage level of the input signal (RX1) from [CH1] CPU (LX2160A) is slightly lower and the EYE is slightly smaller.
    They recognize that the three experiments will confirm whether this EYE is improved and CDR lock is stabilized.

    The "Eye Monitor" screen is added only to [CH1] from line 287.
    It may occur when observing several times with "Single Capture".
    What kind of state is this?
    By the way, it does not occur in [CH0].

    Could you please comment on this condition before the verification experiment?

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thank you for the update.  The eye monitor is dependent on CDR lock, so I would not consider the eye monitor results to be valid for CH1 where CDR is unlocked.

    Regarding the eye measurements where CH1 is locked (line 287), these seem very odd, and do not match the HEO/VEO that the GUI is reporting.  Looking at the "error hit density", it almost looks like the link is down for part of the eye measurement, and up for another part.  This is strange.  Are you observing consistent CDR lock in these configuration?  Is there any configuration difference between CH1 eye measurements at line 197 vs line 287?

    Please try some of the experiments previously recommended and let me know if this improves CH1 CDR lock stability.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi,

    The customer reported the results of the experiment.

    Conclusion, CDR lock was not stable.
    Even with the suggested conditions alone, it didn't work, and even after setting VGA_SEL_GAIN in REG 0x84[0] to "1" and confirming it, the result did not change. (In their environment, CPU VOD was fixed at 300mV, so I recommended setting <600mVppd)

    They say that the retimer HEO seems to be stable, but there are times when the CDR lock is released.

    Attached is the data of the linux shell script created for verification.

    test_01-03_20230217.txttest_01v-03v_20230217.txt
    Please refer to the attached "TESTmemo_20230217.txt" for the verification details.

    Fullscreen TESTmemo_20230217.txt Download 
    25G Retimer TEST�@memo

execution script
// test 01 - 03
./25g_retimer_setup_reset.sh
./25g_retimer_test_xx.sh


// test 01V - 03V
./25g_retimer_setup_reset.sh
./25g_retimer_test_eq_vga_set.sh
./25g_retimer_test_xx.sh


----------------------------------------
Verification environment: Same configuration as TEST 01
�@CPU(LX2160A) --> DS250DF230 --> CPU(LX2160A) : Retimer ch1 side

Verification item

TEST 01
�@Default

TEST 02
�@Adapt Mode = 2 , Enable DFE set

TEST 03
�@Adapt Mode = 2 , Enable DFE set
�@Enable CTLE Bypass set
�@TEST 03-00
�@�@Enable CTLE Bypass : Set CTLE boost to 0x00
�@TEST 03-01
�@�@Enable CTLE Bypass : Set CTLE boost to 0x01
�@TEST 03-02
�@�@Enable CTLE Bypass : Set CTLE boost to 0x02
�@TEST 03-03
�@�@Enable CTLE Bypass : Set CTLE boost to 0x03

Retimer was working with CTLE = 00, so I have not verified setting CTLE manually.

Also, set VGA_SEL_GAIN in REG 0x84[0] to "1" to verify TEST 01 - 03 above.

Attached observation data.
(1)�utest_01-03_20230217.txt�v

(2)�utest_01v-03v_20230217.txt�v
�@�@Test with VGA_SEL_GAIN in REG 0x84[0] set to "1"
�@�@Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode : 11

��About status notation
 cnt : 0120, CH1 SD/CDR Status : 0x30, OK : 0089, -- : 0031, HEO : 0.5938, VEO : 218.7500
 ��
 cnt : 0120,
   Status in 1 second intervals, 1-120 times

 CH1 SD/CDR Status : 0x30, OK : 0089, -- : 0031,
  SD_STATUS and CDR_LOCK_STATUS results on ch1 Reg_0x78
    OK: Cumulative when 0x30 ( -- display when 0x20)
    NG: Cumulative for 0x20 ( -- display is for 0x30)

HEO : 0.5938,
    HEO of ch1 Reg_0x27, To convert HEO to UI: HEO_UI = Reg_0x27 / 32

  VEO : 218.7500
    VEO of ch1 Reg_0x27, To convert VEO to mV: VEO_mV = Reg_0x28 * 3.125
 
----------------------------------------

    In addition, they understood that the EYE Monitor becomes effective when the CDR is locked, so it seems that they did not observe when the CDR lock was not stable.
    If there is any other necessary data or information, we will ask for it.
    I would appreciate it if you could suggest some solution.

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thank you for sharing the verification logs.  Would it be possible to and include register 0x02 in this log?  Register 0x02 includes additional details about CDR lock and which criteria might be gating CDR lock.

    Another question: Does the CPU have either link training or auto-negotiation enabled?  If so, would it be possible to disable these for testing?  The retimer does not support link training since it does not have a linear signal chain.  If auto-negotiation is necessary in the system, it can be supported by enabling CDR bypass for data that cannot be locked to. See section 7.34 of programming guide for this.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi,


    The customer reported the results of the experiment.

    Conclusion, CDR lock was not stable.

    Below is our report on each of your items.

    > - Is it possible to include register 0x02 in this log?
    > > Register 0x02 contains additional details about the CDR lock and the criteria that may be gating the CDR lock.

    ⇒ The following commented part of the attached (

    Fullscreen TEST_memo_20230302.txt Download 
    25G Retimer TESTmemo

----------------------------------------
Reg_0x02[7:0] = CDR_STATUS added
----------------------------------------

Execution script
// test 01 - 03
// test_01-03_reg_0x02_20230224.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_xx2.sh


// test 01V - 03V eq_vga11
// test_01v-03v_reg_0x02_20230224.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_eq_vga_set.sh
./25g_retimer_test_xx2.sh


----------------------------------------
CDR Bypass, Pre-LOCK = Raw Data, Post = Retimed Data
Link Status is on CPU side --> Link NG Yes
----------------------------------------

Execution script
// test 01 - 03
// test_01-03_cdr_bypass_pre_20230224.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_cdr_bypass_pre.sh
./25g_retimer_test_xx3.sh

// test 01V - 03V eq_vga11
// test_01v-03v_cdr_bypass_pre_20230224.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_cdr_bypass_pre.sh
./25g_retimer_test_eq_vga_set.sh
./25g_retimer_test_xx3.sh


----------------------------------------
CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data
Link status is on CPU side --> Link NG Gone
----------------------------------------

Execution script
// test 01 - 03
// test_01-03_cdr_bypass_pre_post_20230224.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_cdr_bypass_pre_post.sh
./25g_retimer_test_xx3.sh

// test 01V - 03V eq_vga11
// test_01v-03v_cdr_bypass_pre_post_20230224.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_cdr_bypass_pre_post.sh
./25g_retimer_test_eq_vga_set.sh
./25g_retimer_test_xx3.sh


----------------------------------------
Changed RS-FEC setting to no FEC setting
No changed
----------------------------------------

Execution script
// test 01 - 03
// test_01-03_reg_0x02_fec_none_20230302.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_xx2.sh


// test 01V - 03V eq_vga11
// test_01v-03v_reg_0x02_fec_none_20230302.txt
./25g_retimer_setup_reset.sh
./25g_retimer_test_eq_vga_set.sh
./25g_retimer_test_xx2.sh
    ) is the relevant log.
    　Reg_0x02[7:0] = CDR_STATUS added.

    > Is link training or auto-negotiation enabled on the CPU?
    > If so, is it possible to disable them for testing purposes?
    > If your system requires it, you can support it by enabling CDR bypass for data that cannot be locked. Please refer to Section 7.34 of the Programming Guide for more information.

    ⇒We have confirmed that link training and auto-negotiation are disabled on the CPU side.
    ⇒As for enabling CDR Bypass, the following comment in the attached file (TEST_memo_20230302.txt) is the corresponding log.
    　CDR Bypass, Pre-LOCK = Raw Data, Post = Retimed Data
    　CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data
    　　--> When both Pre and Post are set to Raw Data, the link state has stabilized.

    ⇒I also tried to enable/disable the FEC function.
    　The following comment in the attached file (TEST_memo_20230302.txt) is the corresponding log.
    　Change the RS-FEC setting to the setting without FEC.

    That is all.
    I am sorry to keep repeating this, but I would appreciate any comments you may have.

    Best Regards,

    test_01-03_cdr_bypass_pre_20230224.txttest_01-03_cdr_bypass_pre_post_20230224.txt

    test_01-03_reg_0x02_20230224.txttest_01v-03v_cdr_bypass_pre_20230224.txt

    test_01v-03v_cdr_bypass_pre_post_20230224.txttest_01v-03v_reg_0x02_20230224.txt

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thanks for the update and thanks for continuing to work through this.  I know this has been ongoing for a while and it has been challenging to identify the root cause.  I'm in the process of looking over the logs and am planning to provide a detailed update tomorrow.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    TI__Mastermind 36043 points

    Hi,

    Sorry about the delay.  Looking over the logs, unfortunately I don't see any clear answers as to why CDR lock loss is being observed.

    I have a couple of thoughts and questions.

    Earlier you had mentioned that in addition to a typical configuration of CPU --> SFP, SFP --> CPU, it is possible to test SFP --> SFP and CPU --> CPU.  Can you clarify in which configurations you're observing link instability?

    Also thank you for confirming that link training and auto-negotiation are disabled on the CPU.  Are these by chance enabled on the link partner?

    One thought I had is to try testing using Adapt mode 0.  This would disable ctle and dfe auto adaptation, so these would need to be manually set.  Looking over the configuration you had previously shared some time ago, it seemed like ctle and dfe were primarily adapting to 0, so this would probably be a reasonable setting.

    A couple other thoughts:

    - After providing an input signal to the retimer, are you providing adequate time for CDR lock prior to reading CDR status?  CDR lock acquisition time is <100ms.

    - Sometimes it can be helpful to hold the retimer CDR in reset while doing any initialization / configuration on the ASIC or module providing signal to the retimer.  Would it be possible to see if this impacts retimer behavior?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hello. Thank you for answering my question.
    I received a response to my proposal and an additional question from a customer.
    They are listed below.

    [Question + Answer.
    (1)>Earlier you had mentioned that in addition to a typical configuration of CPU --> SFP, SFP --> CPU, it is possible to test SFP --> SFP and CPU --> CPU. 

        >Can you clarify in which configurations you're observing link instability?

    (1-answer)
    ⇒ In the CPU → Retimer → SFP and SFP → Retimer → CPU configurations.
    　　Since the link was not working in both directions, we did not enable the crosspoints (in a configuration that is easy to verify)
    　　CPU → Retimer → CPU, SFP → Retimer → SFP configuration.
    　　In this case, the following conditions were achieved
    　　In the direction of SFP → Retimer, CDR Lock is stable and the link is up.
    　　In the direction of CPU → Retimer, CDR Lock is unstable and Link Up is not performed.
    　　

    (2)> Also thank you for confirming that link training and auto-negotiation are disabled on the CPU. 

        >Are these by chance enabled on the link partner?
    　 

    (2-answer)
    ⇒ We are not sure what your question is, but we have both link partners.
    　　Link training and auto-negotiation remain disabled for both link partners.

    (3) > How about testing using Adapt mode 0?
    　  >This would disable ctle and dfe auto adaptation, so these would need to be manually set.  Looking over the configuration you had previously shared some time ago, it seemed like ctle and dfe were primarily adapting to 0, so this would probably be a reasonable setting.

    (3-Answer.)
    ⇒ I have already checked and there is no change in the result.
    　　CDR Lock will remain unstable.

    (4)-After providing an input signal to the retimer, are you providing adequate time for CDR lock prior to reading CDR status? 

         CDR lock acquisition time is <100ms.

    (4-answer)
    ⇒ Yes.
    　　We wait 1 second to read the CDR status.

    (5)> Sometimes it can be helpful to hold the retimer CDR in reset while doing any initialization / configuration on the ASIC or module providing signal to the retimer.  Would it be possible to see if this impacts retimer behavior?

    (5-Answer)
    ⇒ We have already checked and there is no change in the result.
    　　The CDR Lock remains unstable.

    (6- Additional confirmation request)
    Since the Link state was stable in the previous verification, the following verification was performed.
    The following verification was performed.
    > CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data
    > Link state was stable when both Pre and Post were set to Raw Data.

    　　See the attached "TEST_memo20230315" for the test summary.
    　　CPU → Retimer → SFP28 (CH-0)
    　　SFP28 → Retimer → CPU (CH-1)
    　　The only difference in settings between the two configurations is in the following parts.
    　　CH-0
    　　　CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data
    　　CH-1
    　　　CDR Bypass, Pre-LOCK = Mute, Post-LOCK = Retimed data

    　　Since CH-0, CPU → Retimer is set to CDR Bypass, Raw Data, CDR Lock is unstable, but the link partner is in Link Up state.
    　　CH-1, SFP28 → Retimer is in the Link Up state with CDR Lock in the same stable state as before.
    　　With this setting, communication is possible.
    　　CPU <--> Retimer <--> SFP28 <--> 25G Transceiver <--> optical communication <--> PC (25G)

    Looking at the verification results so far, it seems that the CDR Lock instability is caused by a pattern, not a signal level.

    That is all.
    I apologize for repeating myself, but thank you in advance for your patience.

    Fullscreen TEST_memo20230315.txt Download 
    2023.03.15
TEST MEMO

�@Enable crosspoints.
�@�@CPU �� Retimer �� SFP28 (CH-0), SFP28 �� Retimer �� CPU (CH-1) (CH-1) configuration.
�@Link training and auto-negotiation are disabled for both link partners.
�@
  FEC function is disabled for both link partners.
�@
  Script set to Retimer (SFP28 has 2 ports)
�@�@�� The result is Link Up and communication is possible.


�@Execution script
�@�@SFP28 #0
�@�@�@./sfp28_retimer_setup_init.sh 0
�@�@�@./sfp28_retimer_setup_cdr_bypass.sh 0
�@�@�@./sfp28_retimer_setup_cdr_reset.sh 0
�@�@SFP28 #1
�@�@�@./sfp28_retimer_setup_init.sh 1
�@�@�@./sfp28_retimer_setup_cdr_bypass.sh 1
�@�@�@./sfp28_retimer_setup_cdr_reset.sh 1

�@Script Summary
�@ sfp28_retimer_setup_init.sh
�@�@Reset All Channel Registers
�@�@Cross-Point Setup

�@ sfp28_retimer_setup_cdr_bypass.sh
�@�@CH-0
�@�@�@Adapt Mode = 0
�@�@�@CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data
�@�@�@CTLE Boost = 0
�@�@�@EQ gain to 1
�@�@�@VGA Gain to 1
�@�@CH-1
�@�@�@Adapt Mode = 0
�@�@�@CDR Bypass, Pre-LOCK = Mute, Post-LOCK = Retimed data
�@�@�@CTLE Boost = 0
�@�@�@EQ gain to 1
�@�@�@VGA Gain to 1

�@ sfp28_retimer_setup_cdr_reset.sh
�@�@Assert CDR Reset
�@�@1 sec wait
�@�@Release CDR Reset
    Fullscreen sfp28_retimer_setup_cdr_bypass.txt Download 
    #/bin/bash
#
# SFP28(25GbE) Retimer(DS250DF230) Setup(I2C) CDR Bypass
#

# check paramter
    if [ $# -ne 1 ]; then
        echo "Usage: sfp28_retimer_setup_cdr_bypass [port]"
        echo "                                      [port] --> (0:SFP28_0, 1:SFP28_1) $1 "
        exit 1
    fi

# command tmp
    CMD_RT='/tmp/.ess_cmd_rt'


# **************************************************************************************************
    sfp28_port=$1


# **************************************************************************************************
# 25G Retimer I2C Address
# **************************************************************************************************
# i2c-15  i2c  i2c-1-mux (chan_id 2)  I2C adapter  I2C3_CH2  25G Retimer #1
# i2c-16  i2c  i2c-1-mux (chan_id 3)  I2C adapter  I2C3_CH3  25G Retimer #2

# Retimer I2C Address 0x18

    if [ $sfp28_port -eq 0 ]; then
        I2C_ADR="15"
        echo " *** 25G Retimer 0 Setup (CDR Bypass) *** "
    fi
    if [ $sfp28_port -eq 1 ]; then
        I2C_ADR="16"
        echo " *** 25G Retimer 1 Setup (CDR Bypass) *** "
    fi


# **************************************************************************************************
# **********************************************************
# Device ID
# **********************************************************
# ------------------------------------------------------
# Read the Device ID
# ------------------------------------------------------

    i2cget -f -y $I2C_ADR 0x18 0xF1 > $CMD_RT           # Device ID DS250DF230: 0x15
    DATA_TMP="$(cat $CMD_RT)"
    echo " Device ID : $DATA_TMP"


# **********************************************************
# CPU --> Retimer --> SFP28 : CH0
# **********************************************************
# ------------------------------------------------------
# CH0
# ------------------------------------------------------

    echo " CH0"

    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFC 0x01        # Select channel 0
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x01        # Select channel mode

    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x0C        # Assert CDR reset

# ------------------------------------------------------
# Set Receiver Adapt Mode
# ------------------------------------------------------

    echo " Set Receiver Adapt Mode 0"

    i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x00        # Set Adapt Mode = 0
#   i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x20        # Set Adapt Mode = 1
#   i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x40        # Set Adapt Mode = 2
#   i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x40        # Set Adapt Mode = 3

# ------------------------------------------------------
# Select Output Mode When CDR is Not Locked
# Select Output Mode When CDR is Locked
# ------------------------------------------------------

#   echo " Select Output Mode When CDR is Not Locked"
#   echo " Select Output Mode When CDR is Locked"

    echo " CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data"
    i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0x1E 0x00        # PFD_SEL_DATA_PRELCK=3'b000: Raw, un-retimed data
    i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0xA5 0x00        # PFD_SEL_DATA_PSTLCK=3'b000: Raw, un-retimed data

#   echo " CDR Bypass, Pre-LOCK = Raw Data, Post = Retimed Data"
#   i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0x1E 0x00        # PFD_SEL_DATA_PRELCK=3'b000: Raw, un-retimed data

#   echo " CDR Bypass, Pre-LOCK = Mute, Post = Retimed Data"
#   i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0x1E 0xE0        # PFD_SEL_DATA_PRELCK=3'b111: Mute (Default)
#   i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0xA5 0x20        # PFD_SEL_DATA_PSTLCK=3'b001: Retimed data (default)

# ------------------------------------------------------
# Set CTLE Boost Value
# ------------------------------------------------------

    echo " Set CTLE Boost Value"
    i2cset -f -y -m 0x08 $I2C_ADR 0x18 0x2D 0x08        # REG_EQ_BST_OV=1'b1: Enable EQ boost override
    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0x03 0x00        # EQ_BST0-3[1:0]=8'h00: Set EQ boost value as 0

# ------------------------------------------------------
# Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode
# ------------------------------------------------------

# | SOURCE TX LAUNCH AMPLITUDE RANGE    | RECOMMENDED EQ GAIN SETTING | RECOMMENDED VGA GAIN SETTING |
# | < 600 mVppd                         | 1                           | 1                            |
# | 600 - 1000 mVppd                    | 1                           | 0                            |
# | > 1000 mVppd                        | 0                           | 0                            |

    echo " Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode = 11"
    i2cset -f -y -m 0x20 $I2C_ADR 0x18 0x13 0x20        # Set EQ gain to 1
    i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x8E 0x01        # Set VGA Gain to 1

#   echo " Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode = 00"
#   i2cset -f -y -m 0x20 $I2C_ADR 0x18 0x13 0x00        # Set EQ gain to 0
#   i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x8E 0x00        # Set VGA Gain to 0

# ------------------------------------------------------
# Adjustable Output Swing Under Raw Mode
# ------------------------------------------------------

# | RPH(REG_0x1A[7:6]) | Low Swing Mode(REG_0xD[0]=0) | High Swing Mode(REG_0xD[0]=1) |
# | 0                  | 602 mV                       | 733 mV                        |
# | 1                  | 640 mV (Default Setting)     | 782 mV                        |
# | 2                  | 692 mV                       | 846 mV                        |
# | 3                  | 749 mV                       | 919 mV                        | 

#   echo " Adjustable Output Swing Under Raw Mode"
#   i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x0D 0x00        # 0: Low Swing(Default)
#   i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x0D 0x01        # 1: High Swing

#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0x00        # BG_SEL_RPH_LV[1]=1'b0, BG_SEL_RPH_LV[0]=1'b0
#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0x40        # BG_SEL_RPH_LV[1]=1'b0, BG_SEL_RPH_LV[0]=1'b1(Default)
#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0x80        # BG_SEL_RPH_LV[1]=1'b1, BG_SEL_RPH_LV[0]=1'b0
#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0xC0        # BG_SEL_RPH_LV[1]=1'b1, BG_SEL_RPH_LV[0]=1'b1

# ------------------------------------------------------
    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x00        # Release CDR Reset

    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0xFC 0x00        # Select channel X
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x00        # Select shared mode

    sleep 0.5


# **********************************************************
# SFP28 --> Retimer --> CPU : CH1
# **********************************************************
# ------------------------------------------------------
# CH1
# ------------------------------------------------------

    echo " CH1"

    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFC 0x02        # Select channel 1
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x01        # Select channel mode

    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x0C        # Assert CDR reset

# ------------------------------------------------------
# Set Receiver Adapt Mode
# ------------------------------------------------------

    echo " Set Receiver Adapt Mode 0"

    i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x00        # Set Adapt Mode = 0
#   i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x20        # Set Adapt Mode = 1
#   i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x40        # Set Adapt Mode = 2
#   i2cset -f -y -m 0x60 $I2C_ADR 0x18 0x31 0x40        # Set Adapt Mode = 3

# ------------------------------------------------------
# Select Output Mode When CDR is Not Locked
# Select Output Mode When CDR is Locked
# ------------------------------------------------------

#   echo " Select Output Mode When CDR is Not Locked"
#   echo " Select Output Mode When CDR is Locked"

#   echo " CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data"
#   i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0x1E 0x00        # PFD_SEL_DATA_PRELCK=3'b000: Raw, un-retimed data
#   i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0xA5 0x00        # PFD_SEL_DATA_PSTLCK=3'b000: Raw, un-retimed data

#   echo " CDR Bypass, Pre-LOCK = Raw Data, Post = Retimed Data"
#   i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0x1E 0x00        # PFD_SEL_DATA_PRELCK=3'b000: Raw, un-retimed data

    echo " CDR Bypass, Pre-LOCK = Mute, Post = Retimed Data"
    i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0x1E 0xE0        # PFD_SEL_DATA_PRELCK=3'b111: Mute (Default)
    i2cset -f -y -m 0xE0 $I2C_ADR 0x18 0xA5 0x20        # PFD_SEL_DATA_PSTLCK=3'b001: Retimed data (default)

# ------------------------------------------------------
# Set CTLE Boost Value
# ------------------------------------------------------

    echo " Set CTLE Boost Value"
    i2cset -f -y -m 0x08 $I2C_ADR 0x18 0x2D 0x08        # REG_EQ_BST_OV=1'b1: Enable EQ boost override
    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0x03 0x00        # EQ_BST0-3[1:0]=8'h00: Set EQ boost value as 0

# ------------------------------------------------------
# Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode
# ------------------------------------------------------

# | SOURCE TX LAUNCH AMPLITUDE RANGE    | RECOMMENDED EQ GAIN SETTING | RECOMMENDED VGA GAIN SETTING |
# | < 600 mVppd                         | 1                           | 1                            |
# | 600 - 1000 mVppd                    | 1                           | 0                            |
# | > 1000 mVppd                        | 0                           | 0                            |

    echo " Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode = 11"
    i2cset -f -y -m 0x20 $I2C_ADR 0x18 0x13 0x20        # Set EQ gain to 1
    i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x8E 0x01        # Set VGA Gain to 1

#   echo " Set Variable Gain Amplifier (VGA) and CTLE DC Gain Mode = 00"
#   i2cset -f -y -m 0x20 $I2C_ADR 0x18 0x13 0x00        # Set EQ gain to 0
#   i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x8E 0x00        # Set VGA Gain to 0

# ------------------------------------------------------
# Adjustable Output Swing Under Raw Mode
# ------------------------------------------------------

# | RPH(REG_0x1A[7:6]) | Low Swing Mode(REG_0xD[0]=0) | High Swing Mode(REG_0xD[0]=1) |
# | 0                  | 602 mV                       | 733 mV                        |
# | 1                  | 640 mV (Default Setting)     | 782 mV                        |
# | 2                  | 692 mV                       | 846 mV                        |
# | 3                  | 749 mV                       | 919 mV                        | 

#   echo " Adjustable Output Swing Under Raw Mode"
#   i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x0D 0x00        # 0: Low Swing(Default)
#   i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x0D 0x01        # 1: High Swing

#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0x00        # BG_SEL_RPH_LV[1]=1'b0, BG_SEL_RPH_LV[0]=1'b0
#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0x40        # BG_SEL_RPH_LV[1]=1'b0, BG_SEL_RPH_LV[0]=1'b1(Default)
#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0x80        # BG_SEL_RPH_LV[1]=1'b1, BG_SEL_RPH_LV[0]=1'b0
#   i2cset -f -y -m 0xC0 $I2C_ADR 0x18 0x1A 0xC0        # BG_SEL_RPH_LV[1]=1'b1, BG_SEL_RPH_LV[0]=1'b1

# ------------------------------------------------------
    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x00        # Release CDR Reset

    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0xFC 0x00        # Select channel X
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x00        # Select shared mode

    sleep 0.5


# **************************************************************************************************

    echo " *** 25G Retimer Setup END *** "

# **************************************************************************************************


exit 0
    Fullscreen sfp28_retimer_setup_cdr_reset.txt Download 
    #/bin/bash
#
# SFP28(25GbE) Retimer(DS250DF230) Setup(I2C) CDR Reset
#

# check paramter
    if [ $# -ne 1 ]; then
        echo "Usage: sfp28_retimer_setup_cdr_reset [port]"
        echo "                                     [port] --> (0:SFP28_0, 1:SFP28_1) $1 "
        exit 1
    fi

# command tmp
    CMD_RT='/tmp/.ess_cmd_rt'


# **************************************************************************************************
    sfp28_port=$1


# **************************************************************************************************
# 25G Retimer I2C Address
# **************************************************************************************************
# i2c-15  i2c  i2c-1-mux (chan_id 2)  I2C adapter  I2C3_CH2  25G Retimer #1
# i2c-16  i2c  i2c-1-mux (chan_id 3)  I2C adapter  I2C3_CH3  25G Retimer #2

# Retimer I2C Address 0x18

    if [ $sfp28_port -eq 0 ]; then
        I2C_ADR="15"
#       echo " *** 25G Retimer 0 Setup *** "
    fi
    if [ $sfp28_port -eq 1 ]; then
        I2C_ADR="16"
#       echo " *** 25G Retimer 1 Setup *** "
    fi


# **************************************************************************************************

    echo " *** 25G Retimer Setup CDR Reset Start *** "

# **************************************************************************************************

# **********************************************************
# CDR Reset
# **********************************************************

    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFC 0x01        # Select channel 0
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x03        # Select broadcast mode

# ------------------------------------------------------
# Assert CDR Reset
# ------------------------------------------------------

    echo " Assert CDR Reset"

    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x0C        # Assert CDR reset
    sleep 1

# ------------------------------------------------------
# Release CDR Reset
# ------------------------------------------------------

    echo " Release CDR Reset"

    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x00        # Release CDR Reset

    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0xFC 0x00        # Select channel X
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x00        # Select shared mode

    sleep 5


# **************************************************************************************************

    echo " *** 25G Retimer Setup CDR Reset END *** "

# **************************************************************************************************


exit 0
    Fullscreen sfp28_retimer_setup_init.txt Download 
    #/bin/bash
#
# SFP28(25GbE) Retimer(DS250DF230) Setup(I2C) Init
#

# check paramter
    if [ $# -ne 1 ]; then
        echo "Usage: sfp28_retimer_setup_init [port]"
        echo "                                [port] --> (0:SFP28_0, 1:SFP28_1) $1 "
        exit 1
    fi

# command tmp
    CMD_RT='/tmp/.ess_cmd_rt'


# **************************************************************************************************
    sfp28_port=$1


# **************************************************************************************************
# 25G Retimer I2C Address
# **************************************************************************************************
# i2c-15  i2c  i2c-1-mux (chan_id 2)  I2C adapter  I2C3_CH2  25G Retimer #1
# i2c-16  i2c  i2c-1-mux (chan_id 3)  I2C adapter  I2C3_CH3  25G Retimer #2

# Retimer I2C Address 0x18

    if [ $sfp28_port -eq 0 ]; then
        I2C_ADR="15"
#       echo " *** 25G Retimer 0 Setup Init *** "
    fi
    if [ $sfp28_port -eq 1 ]; then
        I2C_ADR="16"
#       echo " *** 25G Retimer 1 Setup Init *** "
    fi


# **************************************************************************************************

    echo " *** 25G Retimer Setup Init Start *** "

# **************************************************************************************************

# **********************************************************
# Device ID
# **********************************************************
# ------------------------------------------------------
# Read the Device ID
# ------------------------------------------------------

    i2cget -f -y $I2C_ADR 0x18 0xF1 > $CMD_RT           # Device ID DS250DF230: 0x15
    DATA_TMP="$(cat $CMD_RT)"
    echo " Device ID : $DATA_TMP"


# **********************************************************
# Reset Channel Registers
# **********************************************************
# ------------------------------------------------------
# Reset All Channel Registers
# ------------------------------------------------------

    echo " Reset All Channel Registers"

    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFC 0x01        # Select channel 0
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x03        # Select broadcast mode

    i2cset -f -y -m 0x04 $I2C_ADR 0x18 0x00 0x04        # Assert channel register reset.
                                                        # This bit is self-clearing.

    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0xFC 0x00        # Select channel X
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x00        # Select shared mode

    sleep 0.5


# **********************************************************
# Configure Cross-Point
# **********************************************************
# ------------------------------------------------------
# Configure Cross-Point CH0
# ------------------------------------------------------

    echo " Configure Cross-Point CH0"

    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFC 0x01        # Select channel 0
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x01        # Select channel mode

    i2cset -f -y -m 0x08 $I2C_ADR 0x18 0x95 0x08        # Set eq_enable to 1
    i2cset -f -y -m 0x08 $I2C_ADR 0x18 0x96 0x00        # Set EQ en_local to 0
    i2cset -f -y -m 0x04 $I2C_ADR 0x18 0x96 0x04        # Set EQ en_fanout to 1
    i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x96 0x00        # Set EQ xpnt_slave to 0
    i2cset -f -y -m 0x02 $I2C_ADR 0x18 0x96 0x02        # Set EQ sel_xpt to 1
    i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x96 0x00        # Set EQ xpnt_slave to 0
    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x0C        # Force CDR Reset
    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x00        # Release CDR Reset

    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0xFC 0x00        # Select channel X
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x00        # Select shared mode


# ------------------------------------------------------
# Configure Cross-Point CH1
# ------------------------------------------------------

    echo " Configure Cross-Point CH1"

    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFC 0x02        # Select channel 1
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x01        # Select channel mode

    i2cset -f -y -m 0x08 $I2C_ADR 0x18 0x95 0x08        # Set eq_enable to 1
    i2cset -f -y -m 0x08 $I2C_ADR 0x18 0x96 0x00        # Set EQ en_local to 0
    i2cset -f -y -m 0x04 $I2C_ADR 0x18 0x96 0x04        # Set EQ en_fanout to 1
    i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x96 0x00        # Set EQ xpnt_slave to 0
    i2cset -f -y -m 0x02 $I2C_ADR 0x18 0x96 0x02        # Set EQ sel_xpt to 1
    i2cset -f -y -m 0x01 $I2C_ADR 0x18 0x96 0x00        # Set EQ xpnt_slave to 0
    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x0C        # Force CDR Reset
    i2cset -f -y -m 0x0C $I2C_ADR 0x18 0x0A 0x00        # Release CDR Reset

    i2cset -f -y -m 0xFF $I2C_ADR 0x18 0xFC 0x00        # Select channel X
    i2cset -f -y -m 0x03 $I2C_ADR 0x18 0xFF 0x00        # Select shared mode

    sleep 1

# **************************************************************************************************

    echo " *** 25G Retimer Setup Init END *** "

# **************************************************************************************************


exit 0

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thanks for the updates and additional details.  

    Okutsu said:
    ⇒ In the CPU → Retimer → SFP and SFP → Retimer → CPU configurations.
    　　Since the link was not working in both directions, we did not enable the crosspoints (in a configuration that is easy to verify)
    　　CPU → Retimer → CPU, SFP → Retimer → SFP configuration.
    　　In this case, the following conditions were achieved
    　　In the direction of SFP → Retimer, CDR Lock is stable and the link is up.
    　　In the direction of CPU → Retimer, CDR Lock is unstable and Link Up is not performed.

    Based on this observation, it seems like the CPU behavior is playing a key role in CDR lock instability since CPU --> retimer --> CPU is unstable while SFP --> retimer --> SFP has stable CDR lock and link is up.  In SFP --> retimer --> CPU, does the retimer have consistent CDR lock?  I'm assuming the in CPU --> retimer --> SFP, CDR lock is unstable.

    You mention that you think there is some pattern dependency to the CDR lock.  Is it possible to transmit just a PRBS pattern from the CPU and see how the retimer behaves?

    I have an additional experiment.  I'm wondering if increase CDR bandwidth might help with CDR lock stability.  Would it be possible to try a couple different CDR bandwidth settings and see how this impacts the CDR lock stability?  Details on CDR bandwidth can be found in section 7.31 of the programming guide.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi,

    Thank you for your reply.

    Our customer's experimental results and confirmations were answered.

    In SFP --> retimer --> CPU, is the CDR lock stable for retimer? In CPU --> retimer --> SFP, I assume that the CDR lock is unstable.

    (Answer.)　
    　　CPU --> Retimer --> SFP28 (Retimer : CH-0)
    　　 : CDR lock unstable, Link state continues
    　　
    SFP28 --> Retimer --> CPU (Retimer : CH-1)
    　　 CDR lock is stable, Link state continues

    　　CPU <--> Retimer <--> SFP28 <--> 25G Transceiver <--> optical communication <--> PC (25G)
    　　25G Transceiver(25GBASE-SR)
    　　Attach the logs during communication.
    　　　

    Fullscreen 4034.sfp28_ping_test_log_01_20230320.txt Download 
    root@jammy-arm64:/home/ubuntu/sfp28# 
root@jammy-arm64:/home/ubuntu/sfp28# ./sfp28_retimer_status.sh 120 0 2

----- status start ----- 2023/03/20 07:12:22 Mon

 cnt : 0001
            CH0 SD/CDR Status : 0x20, -- : 0000, NG : 0001, HEO : 0.0000, VEO : 262.5000, SFP28 OK : 0001, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0001, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0001, -- : 0000
 cnt : 0002
            CH0 SD/CDR Status : 0x30, OK : 0001, -- : 0001, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0002, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0002, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0002, -- : 0000
 cnt : 0003
            CH0 SD/CDR Status : 0x30, OK : 0002, -- : 0001, HEO : 0.4688, VEO :   6.2500, SFP28 OK : 0003, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0003, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0003, -- : 0000
 cnt : 0004
            CH0 SD/CDR Status : 0x30, OK : 0003, -- : 0001, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0004, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0004, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0004, -- : 0000
 cnt : 0005
            CH0 SD/CDR Status : 0x20, -- : 0003, NG : 0002, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0005, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0005, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0005, -- : 0000
 cnt : 0006
            CH0 SD/CDR Status : 0x30, OK : 0004, -- : 0002, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0006, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0006, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0006, -- : 0000
 cnt : 0007
            CH0 SD/CDR Status : 0x20, -- : 0004, NG : 0003, HEO : 0.0938, VEO : 212.5000, SFP28 OK : 0007, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0007, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0007, -- : 0000
 cnt : 0008
            CH0 SD/CDR Status : 0x30, OK : 0005, -- : 0003, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0008, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0008, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0008, -- : 0000
 cnt : 0009
            CH0 SD/CDR Status : 0x30, OK : 0006, -- : 0003, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0009, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0009, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0009, -- : 0000
 cnt : 0010
            CH0 SD/CDR Status : 0x30, OK : 0007, -- : 0003, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0010, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0010, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0010, -- : 0000
 cnt : 0011
            CH0 SD/CDR Status : 0x20, -- : 0007, NG : 0004, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0011, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0011, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0011, -- : 0000
 cnt : 0012
            CH0 SD/CDR Status : 0x30, OK : 0008, -- : 0004, HEO : 0.4688, VEO : 212.5000, SFP28 OK : 0012, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0012, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0012, -- : 0000
 cnt : 0013
            CH0 SD/CDR Status : 0x30, OK : 0009, -- : 0004, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0013, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0013, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0013, -- : 0000
 cnt : 0014
            CH0 SD/CDR Status : 0x30, OK : 0010, -- : 0004, HEO : 0.3750, VEO : 181.2500, SFP28 OK : 0014, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0014, -- : 0000, HEO : 0.4688, VEO : 206.2500, Link  OK : 0014, -- : 0000
 cnt : 0015
            CH0 SD/CDR Status : 0x30, OK : 0011, -- : 0004, HEO : 0.4375, VEO : 243.7500, SFP28 OK : 0015, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0015, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0015, -- : 0000
 cnt : 0016
            CH0 SD/CDR Status : 0x20, -- : 0011, NG : 0005, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0016, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0016, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0016, -- : 0000
 cnt : 0017
            CH0 SD/CDR Status : 0x20, -- : 0011, NG : 0006, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0017, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0017, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0017, -- : 0000
 cnt : 0018
            CH0 SD/CDR Status : 0x30, OK : 0012, -- : 0006, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0018, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0018, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0018, -- : 0000
 cnt : 0019
            CH0 SD/CDR Status : 0x30, OK : 0013, -- : 0006, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0019, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0019, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0019, -- : 0000
 cnt : 0020
            CH0 SD/CDR Status : 0x30, OK : 0014, -- : 0006, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0020, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0020, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0020, -- : 0000
 cnt : 0021
            CH0 SD/CDR Status : 0x30, OK : 0015, -- : 0006, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0021, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0021, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0021, -- : 0000
 cnt : 0022
            CH0 SD/CDR Status : 0x30, OK : 0016, -- : 0006, HEO : 0.4688, VEO : 171.8750, SFP28 OK : 0022, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0022, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0022, -- : 0000
 cnt : 0023
            CH0 SD/CDR Status : 0x20, -- : 0016, NG : 0007, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0023, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0023, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0023, -- : 0000
 cnt : 0024
            CH0 SD/CDR Status : 0x30, OK : 0017, -- : 0007, HEO : 0.4688, VEO : 106.2500, SFP28 OK : 0024, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0024, -- : 0000, HEO : 0.4688, VEO : 206.2500, Link  OK : 0024, -- : 0000
 cnt : 0025
            CH0 SD/CDR Status : 0x30, OK : 0018, -- : 0007, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0025, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0025, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0025, -- : 0000
 cnt : 0026
            CH0 SD/CDR Status : 0x30, OK : 0019, -- : 0007, HEO : 0.4688, VEO : 109.3750, SFP28 OK : 0026, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0026, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0026, -- : 0000
 cnt : 0027
            CH0 SD/CDR Status : 0x30, OK : 0020, -- : 0007, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0027, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0027, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0027, -- : 0000
 cnt : 0028
            CH0 SD/CDR Status : 0x20, -- : 0020, NG : 0008, HEO : 0.0000, VEO : 200.0000, SFP28 OK : 0028, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0028, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0028, -- : 0000
 cnt : 0029
            CH0 SD/CDR Status : 0x20, -- : 0020, NG : 0009, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0029, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0029, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0029, -- : 0000
 cnt : 0030
            CH0 SD/CDR Status : 0x30, OK : 0021, -- : 0009, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0030, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0030, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0030, -- : 0000
 cnt : 0031
            CH0 SD/CDR Status : 0x30, OK : 0022, -- : 0009, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0031, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0031, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0031, -- : 0000
 cnt : 0032
            CH0 SD/CDR Status : 0x20, -- : 0022, NG : 0010, HEO : 0.4375, VEO : 200.0000, SFP28 OK : 0032, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0032, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0032, -- : 0000
 cnt : 0033
            CH0 SD/CDR Status : 0x30, OK : 0023, -- : 0010, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0033, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0033, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0033, -- : 0000
 cnt : 0034
            CH0 SD/CDR Status : 0x20, -- : 0023, NG : 0011, HEO : 0.4375, VEO : 200.0000, SFP28 OK : 0034, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0034, -- : 0000, HEO : 0.4688, VEO : 193.7500, Link  OK : 0034, -- : 0000
 cnt : 0035
            CH0 SD/CDR Status : 0x20, -- : 0023, NG : 0012, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0035, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0035, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0035, -- : 0000
 cnt : 0036
            CH0 SD/CDR Status : 0x30, OK : 0024, -- : 0012, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0036, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0036, -- : 0000, HEO : 0.4688, VEO : 193.7500, Link  OK : 0036, -- : 0000
 cnt : 0037
            CH0 SD/CDR Status : 0x30, OK : 0025, -- : 0012, HEO : 0.4688, VEO : 212.5000, SFP28 OK : 0037, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0037, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0037, -- : 0000
 cnt : 0038
            CH0 SD/CDR Status : 0x20, -- : 0025, NG : 0013, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0038, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0038, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0038, -- : 0000
 cnt : 0039
            CH0 SD/CDR Status : 0x30, OK : 0026, -- : 0013, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0039, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0039, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0039, -- : 0000
 cnt : 0040
            CH0 SD/CDR Status : 0x20, -- : 0026, NG : 0014, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0040, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0040, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0040, -- : 0000
 cnt : 0041
            CH0 SD/CDR Status : 0x30, OK : 0027, -- : 0014, HEO : 0.4688, VEO :   0.0000, SFP28 OK : 0041, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0041, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0041, -- : 0000
 cnt : 0042
            CH0 SD/CDR Status : 0x30, OK : 0028, -- : 0014, HEO : 0.4375, VEO : 237.5000, SFP28 OK : 0042, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0042, -- : 0000, HEO : 0.4688, VEO : 206.2500, Link  OK : 0042, -- : 0000
 cnt : 0043
            CH0 SD/CDR Status : 0x30, OK : 0029, -- : 0014, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0043, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0043, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0043, -- : 0000
 cnt : 0044
            CH0 SD/CDR Status : 0x30, OK : 0030, -- : 0014, HEO : 0.0312, VEO :   6.2500, SFP28 OK : 0044, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0044, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0044, -- : 0000
 cnt : 0045
            CH0 SD/CDR Status : 0x30, OK : 0031, -- : 0014, HEO : 0.4375, VEO : 237.5000, SFP28 OK : 0045, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0045, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0045, -- : 0000
 cnt : 0046
            CH0 SD/CDR Status : 0x20, -- : 0031, NG : 0015, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0046, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0046, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0046, -- : 0000
 cnt : 0047
            CH0 SD/CDR Status : 0x30, OK : 0032, -- : 0015, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0047, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0047, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0047, -- : 0000
 cnt : 0048
            CH0 SD/CDR Status : 0x20, -- : 0032, NG : 0016, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0048, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0048, -- : 0000, HEO : 0.4688, VEO : 193.7500, Link  OK : 0048, -- : 0000
 cnt : 0049
            CH0 SD/CDR Status : 0x30, OK : 0033, -- : 0016, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0049, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0049, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0049, -- : 0000
 cnt : 0050
            CH0 SD/CDR Status : 0x30, OK : 0034, -- : 0016, HEO : 0.4688, VEO :   0.0000, SFP28 OK : 0050, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0050, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0050, -- : 0000
 cnt : 0051
            CH0 SD/CDR Status : 0x30, OK : 0035, -- : 0016, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0051, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0051, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0051, -- : 0000
 cnt : 0052
            CH0 SD/CDR Status : 0x20, -- : 0035, NG : 0017, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0052, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0052, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0052, -- : 0000
 cnt : 0053
            CH0 SD/CDR Status : 0x30, OK : 0036, -- : 0017, HEO : 0.4688, VEO : 150.0000, SFP28 OK : 0053, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0053, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0053, -- : 0000
 cnt : 0054
            CH0 SD/CDR Status : 0x30, OK : 0037, -- : 0017, HEO : 0.4688, VEO : 175.0000, SFP28 OK : 0054, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0054, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0054, -- : 0000
 cnt : 0055
            CH0 SD/CDR Status : 0x30, OK : 0038, -- : 0017, HEO : 0.4688, VEO : 187.5000, SFP28 OK : 0055, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0055, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0055, -- : 0000
 cnt : 0056
            CH0 SD/CDR Status : 0x30, OK : 0039, -- : 0017, HEO : 0.0625, VEO :   0.0000, SFP28 OK : 0056, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0056, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0056, -- : 0000
 cnt : 0057
            CH0 SD/CDR Status : 0x30, OK : 0040, -- : 0017, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0057, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0057, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0057, -- : 0000
 cnt : 0058
            CH0 SD/CDR Status : 0x20, -- : 0040, NG : 0018, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0058, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0058, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0058, -- : 0000
 cnt : 0059
            CH0 SD/CDR Status : 0x30, OK : 0041, -- : 0018, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0059, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0059, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0059, -- : 0000
 cnt : 0060
            CH0 SD/CDR Status : 0x20, -- : 0041, NG : 0019, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0060, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0060, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0060, -- : 0000
 cnt : 0061
            CH0 SD/CDR Status : 0x30, OK : 0042, -- : 0019, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0061, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0061, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0061, -- : 0000
 cnt : 0062
            CH0 SD/CDR Status : 0x30, OK : 0043, -- : 0019, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0062, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0062, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0062, -- : 0000
 cnt : 0063
            CH0 SD/CDR Status : 0x20, -- : 0043, NG : 0020, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0063, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0063, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0063, -- : 0000
 cnt : 0064
            CH0 SD/CDR Status : 0x20, -- : 0043, NG : 0021, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0064, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0064, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0064, -- : 0000
 cnt : 0065
            CH0 SD/CDR Status : 0x30, OK : 0044, -- : 0021, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0065, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0065, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0065, -- : 0000
 cnt : 0066
            CH0 SD/CDR Status : 0x30, OK : 0045, -- : 0021, HEO : 0.4375, VEO : 237.5000, SFP28 OK : 0066, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0066, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0066, -- : 0000
 cnt : 0067
            CH0 SD/CDR Status : 0x20, -- : 0045, NG : 0022, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0067, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0067, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0067, -- : 0000
 cnt : 0068
            CH0 SD/CDR Status : 0x30, OK : 0046, -- : 0022, HEO : 0.3125, VEO : 153.1250, SFP28 OK : 0068, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0068, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0068, -- : 0000
 cnt : 0069
            CH0 SD/CDR Status : 0x20, -- : 0046, NG : 0023, HEO : 0.0000, VEO : 200.0000, SFP28 OK : 0069, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0069, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0069, -- : 0000
 cnt : 0070
            CH0 SD/CDR Status : 0x20, -- : 0046, NG : 0024, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0070, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0070, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0070, -- : 0000
 cnt : 0071
            CH0 SD/CDR Status : 0x30, OK : 0047, -- : 0024, HEO : 0.4688, VEO : 193.7500, SFP28 OK : 0071, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0071, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0071, -- : 0000
 cnt : 0072
            CH0 SD/CDR Status : 0x30, OK : 0048, -- : 0024, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0072, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0072, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0072, -- : 0000
 cnt : 0073
            CH0 SD/CDR Status : 0x20, -- : 0048, NG : 0025, HEO : 0.4375, VEO : 231.2500, SFP28 OK : 0073, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0073, -- : 0000, HEO : 0.4688, VEO : 193.7500, Link  OK : 0073, -- : 0000
 cnt : 0074
            CH0 SD/CDR Status : 0x30, OK : 0049, -- : 0025, HEO : 0.4688, VEO : 212.5000, SFP28 OK : 0074, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0074, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0074, -- : 0000
 cnt : 0075
            CH0 SD/CDR Status : 0x20, -- : 0049, NG : 0026, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0075, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0075, -- : 0000, HEO : 0.4688, VEO : 206.2500, Link  OK : 0075, -- : 0000
 cnt : 0076
            CH0 SD/CDR Status : 0x20, -- : 0049, NG : 0027, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0076, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0076, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0076, -- : 0000
 cnt : 0077
            CH0 SD/CDR Status : 0x30, OK : 0050, -- : 0027, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0077, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0077, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0077, -- : 0000
 cnt : 0078
            CH0 SD/CDR Status : 0x30, OK : 0051, -- : 0027, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0078, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0078, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0078, -- : 0000
 cnt : 0079
            CH0 SD/CDR Status : 0x20, -- : 0051, NG : 0028, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0079, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0079, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0079, -- : 0000
 cnt : 0080
            CH0 SD/CDR Status : 0x30, OK : 0052, -- : 0028, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0080, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0080, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0080, -- : 0000
 cnt : 0081
            CH0 SD/CDR Status : 0x20, -- : 0052, NG : 0029, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0081, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0081, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0081, -- : 0000
 cnt : 0082
            CH0 SD/CDR Status : 0x20, -- : 0052, NG : 0030, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0082, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0082, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0082, -- : 0000
 cnt : 0083
            CH0 SD/CDR Status : 0x30, OK : 0053, -- : 0030, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0083, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0083, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0083, -- : 0000
 cnt : 0084
            CH0 SD/CDR Status : 0x30, OK : 0054, -- : 0030, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0084, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0084, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0084, -- : 0000
 cnt : 0085
            CH0 SD/CDR Status : 0x20, -- : 0054, NG : 0031, HEO : 0.4375, VEO : 200.0000, SFP28 OK : 0085, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0085, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0085, -- : 0000
 cnt : 0086
            CH0 SD/CDR Status : 0x30, OK : 0055, -- : 0031, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0086, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0086, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0086, -- : 0000
 cnt : 0087
            CH0 SD/CDR Status : 0x20, -- : 0055, NG : 0032, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0087, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0087, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0087, -- : 0000
 cnt : 0088
            CH0 SD/CDR Status : 0x30, OK : 0056, -- : 0032, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0088, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0088, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0088, -- : 0000
 cnt : 0089
            CH0 SD/CDR Status : 0x30, OK : 0057, -- : 0032, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0089, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0089, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0089, -- : 0000
 cnt : 0090
            CH0 SD/CDR Status : 0x30, OK : 0058, -- : 0032, HEO : 0.4375, VEO : 237.5000, SFP28 OK : 0090, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0090, -- : 0000, HEO : 0.4688, VEO : 206.2500, Link  OK : 0090, -- : 0000
 cnt : 0091
            CH0 SD/CDR Status : 0x20, -- : 0058, NG : 0033, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0091, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0091, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0091, -- : 0000
 cnt : 0092
            CH0 SD/CDR Status : 0x30, OK : 0059, -- : 0033, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0092, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0092, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0092, -- : 0000
 cnt : 0093
            CH0 SD/CDR Status : 0x20, -- : 0059, NG : 0034, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0093, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0093, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0093, -- : 0000
 cnt : 0094
            CH0 SD/CDR Status : 0x30, OK : 0060, -- : 0034, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0094, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0094, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0094, -- : 0000
 cnt : 0095
            CH0 SD/CDR Status : 0x30, OK : 0061, -- : 0034, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0095, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0095, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0095, -- : 0000
 cnt : 0096
            CH0 SD/CDR Status : 0x30, OK : 0062, -- : 0034, HEO : 0.4688, VEO : 212.5000, SFP28 OK : 0096, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0096, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0096, -- : 0000
 cnt : 0097
            CH0 SD/CDR Status : 0x20, -- : 0062, NG : 0035, HEO : 0.0625, VEO :   6.2500, SFP28 OK : 0097, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0097, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0097, -- : 0000
 cnt : 0098
            CH0 SD/CDR Status : 0x30, OK : 0063, -- : 0035, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0098, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0098, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0098, -- : 0000
 cnt : 0099
            CH0 SD/CDR Status : 0x20, -- : 0063, NG : 0036, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0099, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0099, -- : 0000, HEO : 0.4688, VEO : 193.7500, Link  OK : 0099, -- : 0000
 cnt : 0100
            CH0 SD/CDR Status : 0x30, OK : 0064, -- : 0036, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0100, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0100, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0100, -- : 0000
 cnt : 0101
            CH0 SD/CDR Status : 0x20, -- : 0064, NG : 0037, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0101, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0101, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0101, -- : 0000
 cnt : 0102
            CH0 SD/CDR Status : 0x30, OK : 0065, -- : 0037, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0102, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0102, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0102, -- : 0000
 cnt : 0103
            CH0 SD/CDR Status : 0x30, OK : 0066, -- : 0037, HEO : 0.0625, VEO :   0.0000, SFP28 OK : 0103, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0103, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0103, -- : 0000
 cnt : 0104
            CH0 SD/CDR Status : 0x30, OK : 0067, -- : 0037, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0104, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0104, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0104, -- : 0000
 cnt : 0105
            CH0 SD/CDR Status : 0x20, -- : 0067, NG : 0038, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0105, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0105, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0105, -- : 0000
 cnt : 0106
            CH0 SD/CDR Status : 0x30, OK : 0068, -- : 0038, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0106, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0106, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0106, -- : 0000
 cnt : 0107
            CH0 SD/CDR Status : 0x20, -- : 0068, NG : 0039, HEO : 0.0625, VEO : 231.2500, SFP28 OK : 0107, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0107, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0107, -- : 0000
 cnt : 0108
            CH0 SD/CDR Status : 0x30, OK : 0069, -- : 0039, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0108, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0108, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0108, -- : 0000
 cnt : 0109
            CH0 SD/CDR Status : 0x30, OK : 0070, -- : 0039, HEO : 0.4688, VEO :   0.0000, SFP28 OK : 0109, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0109, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0109, -- : 0000
 cnt : 0110
            CH0 SD/CDR Status : 0x30, OK : 0071, -- : 0039, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0110, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0110, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0110, -- : 0000
 cnt : 0111
            CH0 SD/CDR Status : 0x20, -- : 0071, NG : 0040, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0111, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0111, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0111, -- : 0000
 cnt : 0112
            CH0 SD/CDR Status : 0x30, OK : 0072, -- : 0040, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0112, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0112, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0112, -- : 0000
 cnt : 0113
            CH0 SD/CDR Status : 0x20, -- : 0072, NG : 0041, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0113, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0113, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0113, -- : 0000
 cnt : 0114
            CH0 SD/CDR Status : 0x30, OK : 0073, -- : 0041, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0114, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0114, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0114, -- : 0000
 cnt : 0115
            CH0 SD/CDR Status : 0x30, OK : 0074, -- : 0041, HEO : 0.4688, VEO :  12.5000, SFP28 OK : 0115, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0115, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0115, -- : 0000
 cnt : 0116
            CH0 SD/CDR Status : 0x30, OK : 0075, -- : 0041, HEO : 0.4688, VEO : 206.2500, SFP28 OK : 0116, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0116, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0116, -- : 0000
 cnt : 0117
            CH0 SD/CDR Status : 0x20, -- : 0075, NG : 0042, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0117, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0117, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0117, -- : 0000
 cnt : 0118
            CH0 SD/CDR Status : 0x30, OK : 0076, -- : 0042, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0118, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0118, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0118, -- : 0000
 cnt : 0119
            CH0 SD/CDR Status : 0x20, -- : 0076, NG : 0043, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0119, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0119, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0119, -- : 0000
 cnt : 0120
            CH0 SD/CDR Status : 0x30, OK : 0077, -- : 0043, HEO : 0.4688, VEO : 212.5000, SFP28 OK : 0120, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0120, -- : 0000, HEO : 0.4688, VEO : 200.0000, Link  OK : 0120, -- : 0000
root@jammy-arm64:/home/ubuntu/sfp28# 
root@jammy-arm64:/home/ubuntu/sfp28# 
root@jammy-arm64:/home/ubuntu/sfp28# ./sfp28_retimer_status.sh 120 1 2

----- status start ----- 2023/03/20 07:15:15 Mon

 cnt : 0001
            CH0 SD/CDR Status : 0x20, -- : 0000, NG : 0001, HEO : 0.0625, VEO :   6.2500, SFP28 OK : 0001, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0001, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0001, -- : 0000
 cnt : 0002
            CH0 SD/CDR Status : 0x20, -- : 0000, NG : 0002, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0002, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0002, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0002, -- : 0000
 cnt : 0003
            CH0 SD/CDR Status : 0x30, OK : 0001, -- : 0002, HEO : 0.5000, VEO : 237.5000, SFP28 OK : 0003, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0003, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0003, -- : 0000
 cnt : 0004
            CH0 SD/CDR Status : 0x30, OK : 0002, -- : 0002, HEO : 0.5000, VEO :   0.0000, SFP28 OK : 0004, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0004, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0004, -- : 0000
 cnt : 0005
            CH0 SD/CDR Status : 0x20, -- : 0002, NG : 0003, HEO : 0.5000, VEO : 200.0000, SFP28 OK : 0005, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0005, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0005, -- : 0000
 cnt : 0006
            CH0 SD/CDR Status : 0x30, OK : 0003, -- : 0003, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0006, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0006, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0006, -- : 0000
 cnt : 0007
            CH0 SD/CDR Status : 0x20, -- : 0003, NG : 0004, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0007, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0007, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0007, -- : 0000
 cnt : 0008
            CH0 SD/CDR Status : 0x30, OK : 0004, -- : 0004, HEO : 0.5000, VEO : 237.5000, SFP28 OK : 0008, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0008, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0008, -- : 0000
 cnt : 0009
            CH0 SD/CDR Status : 0x20, -- : 0004, NG : 0005, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0009, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0009, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0009, -- : 0000
 cnt : 0010
            CH0 SD/CDR Status : 0x30, OK : 0005, -- : 0005, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0010, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0010, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0010, -- : 0000
 cnt : 0011
            CH0 SD/CDR Status : 0x30, OK : 0006, -- : 0005, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0011, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0011, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0011, -- : 0000
 cnt : 0012
            CH0 SD/CDR Status : 0x20, -- : 0006, NG : 0006, HEO : 0.0000, VEO : 200.0000, SFP28 OK : 0012, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0012, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0012, -- : 0000
 cnt : 0013
            CH0 SD/CDR Status : 0x30, OK : 0007, -- : 0006, HEO : 0.5000, VEO :   0.0000, SFP28 OK : 0013, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0013, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0013, -- : 0000
 cnt : 0014
            CH0 SD/CDR Status : 0x20, -- : 0007, NG : 0007, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0014, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0014, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0014, -- : 0000
 cnt : 0015
            CH0 SD/CDR Status : 0x30, OK : 0008, -- : 0007, HEO : 0.5000, VEO : 206.2500, SFP28 OK : 0015, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0015, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0015, -- : 0000
 cnt : 0016
            CH0 SD/CDR Status : 0x30, OK : 0009, -- : 0007, HEO : 0.4688, VEO : 231.2500, SFP28 OK : 0016, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0016, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0016, -- : 0000
 cnt : 0017
            CH0 SD/CDR Status : 0x20, -- : 0009, NG : 0008, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0017, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0017, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0017, -- : 0000
 cnt : 0018
            CH0 SD/CDR Status : 0x20, -- : 0009, NG : 0009, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0018, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0018, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0018, -- : 0000
 cnt : 0019
            CH0 SD/CDR Status : 0x30, OK : 0010, -- : 0009, HEO : 0.5000, VEO : 212.5000, SFP28 OK : 0019, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0019, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0019, -- : 0000
 cnt : 0020
            CH0 SD/CDR Status : 0x20, -- : 0010, NG : 0010, HEO : 0.0625, VEO : 200.0000, SFP28 OK : 0020, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0020, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0020, -- : 0000
 cnt : 0021
            CH0 SD/CDR Status : 0x30, OK : 0011, -- : 0010, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0021, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0021, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0021, -- : 0000
 cnt : 0022
            CH0 SD/CDR Status : 0x20, -- : 0011, NG : 0011, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0022, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0022, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0022, -- : 0000
 cnt : 0023
            CH0 SD/CDR Status : 0x30, OK : 0012, -- : 0011, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0023, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0023, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0023, -- : 0000
 cnt : 0024
            CH0 SD/CDR Status : 0x30, OK : 0013, -- : 0011, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0024, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0024, -- : 0000, HEO : 0.5312, VEO : 225.0000, Link  OK : 0024, -- : 0000
 cnt : 0025
            CH0 SD/CDR Status : 0x20, -- : 0013, NG : 0012, HEO : 0.0312, VEO : 243.7500, SFP28 OK : 0025, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0025, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0025, -- : 0000
 cnt : 0026
            CH0 SD/CDR Status : 0x30, OK : 0014, -- : 0012, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0026, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0026, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0026, -- : 0000
 cnt : 0027
            CH0 SD/CDR Status : 0x20, -- : 0014, NG : 0013, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0027, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0027, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0027, -- : 0000
 cnt : 0028
            CH0 SD/CDR Status : 0x30, OK : 0015, -- : 0013, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0028, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0028, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0028, -- : 0000
 cnt : 0029
            CH0 SD/CDR Status : 0x20, -- : 0015, NG : 0014, HEO : 0.0312, VEO : 231.2500, SFP28 OK : 0029, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0029, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0029, -- : 0000
 cnt : 0030
            CH0 SD/CDR Status : 0x30, OK : 0016, -- : 0014, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0030, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0030, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0030, -- : 0000
 cnt : 0031
            CH0 SD/CDR Status : 0x30, OK : 0017, -- : 0014, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0031, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0031, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0031, -- : 0000
 cnt : 0032
            CH0 SD/CDR Status : 0x20, -- : 0017, NG : 0015, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0032, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0032, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0032, -- : 0000
 cnt : 0033
            CH0 SD/CDR Status : 0x20, -- : 0017, NG : 0016, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0033, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0033, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0033, -- : 0000
 cnt : 0034
            CH0 SD/CDR Status : 0x30, OK : 0018, -- : 0016, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0034, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0034, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0034, -- : 0000
 cnt : 0035
            CH0 SD/CDR Status : 0x30, OK : 0019, -- : 0016, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0035, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0035, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0035, -- : 0000
 cnt : 0036
            CH0 SD/CDR Status : 0x20, -- : 0019, NG : 0017, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0036, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0036, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0036, -- : 0000
 cnt : 0037
            CH0 SD/CDR Status : 0x30, OK : 0020, -- : 0017, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0037, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0037, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0037, -- : 0000
 cnt : 0038
            CH0 SD/CDR Status : 0x20, -- : 0020, NG : 0018, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0038, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0038, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0038, -- : 0000
 cnt : 0039
            CH0 SD/CDR Status : 0x30, OK : 0021, -- : 0018, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0039, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0039, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0039, -- : 0000
 cnt : 0040
            CH0 SD/CDR Status : 0x30, OK : 0022, -- : 0018, HEO : 0.0938, VEO :  12.5000, SFP28 OK : 0040, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0040, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0040, -- : 0000
 cnt : 0041
            CH0 SD/CDR Status : 0x30, OK : 0023, -- : 0018, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0041, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0041, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0041, -- : 0000
 cnt : 0042
            CH0 SD/CDR Status : 0x30, OK : 0024, -- : 0018, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0042, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0042, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0042, -- : 0000
 cnt : 0043
            CH0 SD/CDR Status : 0x20, -- : 0024, NG : 0019, HEO : 0.5000, VEO : 200.0000, SFP28 OK : 0043, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0043, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0043, -- : 0000
 cnt : 0044
            CH0 SD/CDR Status : 0x20, -- : 0024, NG : 0020, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0044, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0044, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0044, -- : 0000
 cnt : 0045
            CH0 SD/CDR Status : 0x30, OK : 0025, -- : 0020, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0045, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0045, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0045, -- : 0000
 cnt : 0046
            CH0 SD/CDR Status : 0x30, OK : 0026, -- : 0020, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0046, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0046, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0046, -- : 0000
 cnt : 0047
            CH0 SD/CDR Status : 0x30, OK : 0027, -- : 0020, HEO : 0.5000, VEO :   0.0000, SFP28 OK : 0047, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0047, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0047, -- : 0000
 cnt : 0048
            CH0 SD/CDR Status : 0x30, OK : 0028, -- : 0020, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0048, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0048, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0048, -- : 0000
 cnt : 0049
            CH0 SD/CDR Status : 0x20, -- : 0028, NG : 0021, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0049, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0049, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0049, -- : 0000
 cnt : 0050
            CH0 SD/CDR Status : 0x30, OK : 0029, -- : 0021, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0050, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0050, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0050, -- : 0000
 cnt : 0051
            CH0 SD/CDR Status : 0x30, OK : 0030, -- : 0021, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0051, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0051, -- : 0000, HEO : 0.5312, VEO : 225.0000, Link  OK : 0051, -- : 0000
 cnt : 0052
            CH0 SD/CDR Status : 0x20, -- : 0030, NG : 0022, HEO : 0.0625, VEO : 225.0000, SFP28 OK : 0052, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0052, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0052, -- : 0000
 cnt : 0053
            CH0 SD/CDR Status : 0x30, OK : 0031, -- : 0022, HEO : 0.5000, VEO : 212.5000, SFP28 OK : 0053, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0053, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0053, -- : 0000
 cnt : 0054
            CH0 SD/CDR Status : 0x20, -- : 0031, NG : 0023, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0054, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0054, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0054, -- : 0000
 cnt : 0055
            CH0 SD/CDR Status : 0x30, OK : 0032, -- : 0023, HEO : 0.4688, VEO :   0.0000, SFP28 OK : 0055, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0055, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0055, -- : 0000
 cnt : 0056
            CH0 SD/CDR Status : 0x20, -- : 0032, NG : 0024, HEO : 0.5000, VEO : 212.5000, SFP28 OK : 0056, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0056, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0056, -- : 0000
 cnt : 0057
            CH0 SD/CDR Status : 0x30, OK : 0033, -- : 0024, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0057, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0057, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0057, -- : 0000
 cnt : 0058
            CH0 SD/CDR Status : 0x30, OK : 0034, -- : 0024, HEO : 0.5000, VEO : 212.5000, SFP28 OK : 0058, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0058, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0058, -- : 0000
 cnt : 0059
            CH0 SD/CDR Status : 0x20, -- : 0034, NG : 0025, HEO : 0.5000, VEO : 200.0000, SFP28 OK : 0059, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0059, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0059, -- : 0000
 cnt : 0060
            CH0 SD/CDR Status : 0x20, -- : 0034, NG : 0026, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0060, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0060, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0060, -- : 0000
 cnt : 0061
            CH0 SD/CDR Status : 0x30, OK : 0035, -- : 0026, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0061, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0061, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0061, -- : 0000
 cnt : 0062
            CH0 SD/CDR Status : 0x30, OK : 0036, -- : 0026, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0062, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0062, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0062, -- : 0000
 cnt : 0063
            CH0 SD/CDR Status : 0x20, -- : 0036, NG : 0027, HEO : 0.0625, VEO :   6.2500, SFP28 OK : 0063, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0063, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0063, -- : 0000
 cnt : 0064
            CH0 SD/CDR Status : 0x30, OK : 0037, -- : 0027, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0064, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0064, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0064, -- : 0000
 cnt : 0065
            CH0 SD/CDR Status : 0x20, -- : 0037, NG : 0028, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0065, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0065, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0065, -- : 0000
 cnt : 0066
            CH0 SD/CDR Status : 0x30, OK : 0038, -- : 0028, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0066, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0066, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0066, -- : 0000
 cnt : 0067
            CH0 SD/CDR Status : 0x30, OK : 0039, -- : 0028, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0067, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0067, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0067, -- : 0000
 cnt : 0068
            CH0 SD/CDR Status : 0x30, OK : 0040, -- : 0028, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0068, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0068, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0068, -- : 0000
 cnt : 0069
            CH0 SD/CDR Status : 0x30, OK : 0041, -- : 0028, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0069, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0069, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0069, -- : 0000
 cnt : 0070
            CH0 SD/CDR Status : 0x20, -- : 0041, NG : 0029, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0070, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0070, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0070, -- : 0000
 cnt : 0071
            CH0 SD/CDR Status : 0x30, OK : 0042, -- : 0029, HEO : 0.0625, VEO :   0.0000, SFP28 OK : 0071, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0071, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0071, -- : 0000
 cnt : 0072
            CH0 SD/CDR Status : 0x20, -- : 0042, NG : 0030, HEO : 0.0312, VEO : 218.7500, SFP28 OK : 0072, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0072, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0072, -- : 0000
 cnt : 0073
            CH0 SD/CDR Status : 0x30, OK : 0043, -- : 0030, HEO : 0.4062, VEO : 256.2500, SFP28 OK : 0073, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0073, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0073, -- : 0000
 cnt : 0074
            CH0 SD/CDR Status : 0x30, OK : 0044, -- : 0030, HEO : 0.4688, VEO : 225.0000, SFP28 OK : 0074, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0074, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0074, -- : 0000
 cnt : 0075
            CH0 SD/CDR Status : 0x20, -- : 0044, NG : 0031, HEO : 0.5000, VEO : 200.0000, SFP28 OK : 0075, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0075, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0075, -- : 0000
 cnt : 0076
            CH0 SD/CDR Status : 0x30, OK : 0045, -- : 0031, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0076, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0076, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0076, -- : 0000
 cnt : 0077
            CH0 SD/CDR Status : 0x30, OK : 0046, -- : 0031, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0077, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0077, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0077, -- : 0000
 cnt : 0078
            CH0 SD/CDR Status : 0x30, OK : 0047, -- : 0031, HEO : 0.5000, VEO :   0.0000, SFP28 OK : 0078, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0078, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0078, -- : 0000
 cnt : 0079
            CH0 SD/CDR Status : 0x20, -- : 0047, NG : 0032, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0079, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0079, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0079, -- : 0000
 cnt : 0080
            CH0 SD/CDR Status : 0x20, -- : 0047, NG : 0033, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0080, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0080, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0080, -- : 0000
 cnt : 0081
            CH0 SD/CDR Status : 0x30, OK : 0048, -- : 0033, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0081, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0081, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0081, -- : 0000
 cnt : 0082
            CH0 SD/CDR Status : 0x30, OK : 0049, -- : 0033, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0082, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0082, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0082, -- : 0000
 cnt : 0083
            CH0 SD/CDR Status : 0x20, -- : 0049, NG : 0034, HEO : 0.0625, VEO :  25.0000, SFP28 OK : 0083, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0083, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0083, -- : 0000
 cnt : 0084
            CH0 SD/CDR Status : 0x30, OK : 0050, -- : 0034, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0084, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0084, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0084, -- : 0000
 cnt : 0085
            CH0 SD/CDR Status : 0x20, -- : 0050, NG : 0035, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0085, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0085, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0085, -- : 0000
 cnt : 0086
            CH0 SD/CDR Status : 0x30, OK : 0051, -- : 0035, HEO : 0.5000, VEO : 237.5000, SFP28 OK : 0086, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0086, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0086, -- : 0000
 cnt : 0087
            CH0 SD/CDR Status : 0x30, OK : 0052, -- : 0035, HEO : 0.0625, VEO :   0.0000, SFP28 OK : 0087, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0087, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0087, -- : 0000
 cnt : 0088
            CH0 SD/CDR Status : 0x30, OK : 0053, -- : 0035, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0088, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0088, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0088, -- : 0000
 cnt : 0089
            CH0 SD/CDR Status : 0x30, OK : 0054, -- : 0035, HEO : 0.5000, VEO : 237.5000, SFP28 OK : 0089, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0089, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0089, -- : 0000
 cnt : 0090
            CH0 SD/CDR Status : 0x20, -- : 0054, NG : 0036, HEO : 0.4688, VEO : 200.0000, SFP28 OK : 0090, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0090, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0090, -- : 0000
 cnt : 0091
            CH0 SD/CDR Status : 0x20, -- : 0054, NG : 0037, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0091, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0091, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0091, -- : 0000
 cnt : 0092
            CH0 SD/CDR Status : 0x30, OK : 0055, -- : 0037, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0092, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0092, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0092, -- : 0000
 cnt : 0093
            CH0 SD/CDR Status : 0x30, OK : 0056, -- : 0037, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0093, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0093, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0093, -- : 0000
 cnt : 0094
            CH0 SD/CDR Status : 0x30, OK : 0057, -- : 0037, HEO : 0.0625, VEO :   0.0000, SFP28 OK : 0094, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0094, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0094, -- : 0000
 cnt : 0095
            CH0 SD/CDR Status : 0x30, OK : 0058, -- : 0037, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0095, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0095, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0095, -- : 0000
 cnt : 0096
            CH0 SD/CDR Status : 0x20, -- : 0058, NG : 0038, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0096, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0096, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0096, -- : 0000
 cnt : 0097
            CH0 SD/CDR Status : 0x30, OK : 0059, -- : 0038, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0097, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0097, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0097, -- : 0000
 cnt : 0098
            CH0 SD/CDR Status : 0x30, OK : 0060, -- : 0038, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0098, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0098, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0098, -- : 0000
 cnt : 0099
            CH0 SD/CDR Status : 0x30, OK : 0061, -- : 0038, HEO : 0.4375, VEO : 218.7500, SFP28 OK : 0099, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0099, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0099, -- : 0000
 cnt : 0100
            CH0 SD/CDR Status : 0x30, OK : 0062, -- : 0038, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0100, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0100, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0100, -- : 0000
 cnt : 0101
            CH0 SD/CDR Status : 0x20, -- : 0062, NG : 0039, HEO : 0.0000, VEO : 200.0000, SFP28 OK : 0101, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0101, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0101, -- : 0000
 cnt : 0102
            CH0 SD/CDR Status : 0x30, OK : 0063, -- : 0039, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0102, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0102, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0102, -- : 0000
 cnt : 0103
            CH0 SD/CDR Status : 0x20, -- : 0063, NG : 0040, HEO : 0.4688, VEO : 225.0000, SFP28 OK : 0103, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0103, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0103, -- : 0000
 cnt : 0104
            CH0 SD/CDR Status : 0x30, OK : 0064, -- : 0040, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0104, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0104, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0104, -- : 0000
 cnt : 0105
            CH0 SD/CDR Status : 0x20, -- : 0064, NG : 0041, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0105, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0105, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0105, -- : 0000
 cnt : 0106
            CH0 SD/CDR Status : 0x20, -- : 0064, NG : 0042, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0106, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0106, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0106, -- : 0000
 cnt : 0107
            CH0 SD/CDR Status : 0x20, -- : 0064, NG : 0043, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0107, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0107, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0107, -- : 0000
 cnt : 0108
            CH0 SD/CDR Status : 0x30, OK : 0065, -- : 0043, HEO : 0.5000, VEO : 225.0000, SFP28 OK : 0108, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0108, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0108, -- : 0000
 cnt : 0109
            CH0 SD/CDR Status : 0x30, OK : 0066, -- : 0043, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0109, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0109, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0109, -- : 0000
 cnt : 0110
            CH0 SD/CDR Status : 0x20, -- : 0066, NG : 0044, HEO : 0.0312, VEO :   0.0000, SFP28 OK : 0110, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0110, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0110, -- : 0000
 cnt : 0111
            CH0 SD/CDR Status : 0x30, OK : 0067, -- : 0044, HEO : 0.4688, VEO : 231.2500, SFP28 OK : 0111, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0111, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0111, -- : 0000
 cnt : 0112
            CH0 SD/CDR Status : 0x20, -- : 0067, NG : 0045, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0112, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0112, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0112, -- : 0000
 cnt : 0113
            CH0 SD/CDR Status : 0x30, OK : 0068, -- : 0045, HEO : 0.5000, VEO : 231.2500, SFP28 OK : 0113, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0113, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0113, -- : 0000
 cnt : 0114
            CH0 SD/CDR Status : 0x30, OK : 0069, -- : 0045, HEO : 0.5000, VEO : 218.7500, SFP28 OK : 0114, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0114, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0114, -- : 0000
 cnt : 0115
            CH0 SD/CDR Status : 0x20, -- : 0069, NG : 0046, HEO : 0.0625, VEO : 218.7500, SFP28 OK : 0115, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0115, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0115, -- : 0000
 cnt : 0116
            CH0 SD/CDR Status : 0x30, OK : 0070, -- : 0046, HEO : 0.5000, VEO : 212.5000, SFP28 OK : 0116, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0116, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0116, -- : 0000
 cnt : 0117
            CH0 SD/CDR Status : 0x20, -- : 0070, NG : 0047, HEO : 0.0000, VEO :   0.0000, SFP28 OK : 0117, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0117, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0117, -- : 0000
 cnt : 0118
            CH0 SD/CDR Status : 0x30, OK : 0071, -- : 0047, HEO : 0.4688, VEO : 218.7500, SFP28 OK : 0118, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0118, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0118, -- : 0000
 cnt : 0119
            CH0 SD/CDR Status : 0x20, -- : 0071, NG : 0048, HEO : 0.0312, VEO :   6.2500, SFP28 OK : 0119, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0119, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0119, -- : 0000
 cnt : 0120
            CH0 SD/CDR Status : 0x30, OK : 0072, -- : 0048, HEO : 0.3750, VEO : 275.0000, SFP28 OK : 0120, -- : 0000
            CH1 SD/CDR Status : 0x30, OK : 0120, -- : 0000, HEO : 0.5312, VEO : 218.7500, Link  OK : 0120, -- : 0000
root@jammy-arm64:/home/ubuntu/sfp28# 
root@jammy-arm64:/home/ubuntu/sfp28# 
root@jammy-arm64:/home/ubuntu/sfp28#

    　　　Execution script
    　　　. /sfp28_retimer_status.sh 120 0 2 (SFP28 #0 port)
    　　　. /sfp28_retimer_status.sh 120 1 2 (SFP28 #1 port)

    　　Output direction (CH 0)
    　　　CPU --> Retimer
    　　　　Monitor SD/CDR Status, HEO, VEO of Retimer
    　　　Retimer --> SFP28
    　　　　SFP28 side monitors CDR Lock status in 25G Transceiver
    　　Input direction (CH 1)
    　　　SFP28 --> Retimer
    　　　　Monitor SD/CDR Status, HEO, VEO of Retimer
    　　　Retimer --> CPU
    　　　　CPU side monitors MAC (PCS) layer Link status


    You mentioned that you think there is a pattern dependency in CDR locking.

    (Answer.)
    　We do not know.
    　It just appears to be periodic when the CDR lock is released.

    (Question)
    Is it possible to check the behavior of the retimer by sending only the PRBS pattern from the CPU?

    (Answer)
    ⇒ The verification environment is the same as the following test we have been doing.
    　　CPU --> Retimer --> Retimer
    　　SFP28 --> Retimer --> SFP28
    　　Link training and auto-negotiation are disabled.
    　　No FEC

    　　Observe CDR lock status of CPU --> Retimer
    　　　test_01-03
    　　　test 01V - 03V (with eq_vga = 11)

    　　In this test, only 7 PRBS patterns were sent from CPU.
    　　Attached is the result of observing the CDR lock status.
    　　(See

    Fullscreen 6786.TESTmemo_cdr_bandwidth_20230320.txt Download 
    25G Retimer TEST memo

Charge Pump Settings
# ------------------------------------------------------
# Adjust CDR Bandwidth and Charge Pump
# ------------------------------------------------------
# Force CP = 5 , 1C = 0x00, 9E = 0xB4
# Force CP = 6 , 1C = 0x00, 9E = 0xD8
# Force CP = 7 , 1C = 0x00, 9E = 0xFC
# Force CP = 8 , 1C = 0x24, 9E = 0x00
# Force CP = 9 , 1C = 0x24, 9E = 0x24
# Force CP = 10 , 1C = 0x24, 9E = 0x48
# Force CP = 11 , 1C = 0x24, 9E = 0x6C
# Force CP = 12 , 1C = 0x24, 9E = 0x90
# Force CP = 13 , 1C = 0x24, 9E = 0xB4
# Force CP = 14 , 1C = 0x24, 9E = 0xD8
# Force CP = 15 , 1C = 0x24, 9E = 0xFC
# Force CP = 16 , 1C = 0x48, 9E = 0x00


# ------------------------------------------------------
# CDR Bandwidth 01
# ------------------------------------------------------
Verification configuration: as in TEST 01 configuration
�@CPU(LX2160A) --> DS250DF230 --> CPU(LX2160A)
�@Retimer ch1 side setting and observation
�@Observation of CDR lock status for 120 seconds

Verification items

�@TEST 01
�@�@Leave as default
�@�@Observation with Charge Pump set to 5-16

�@TEST 02
�@�@Set Adapt Mode = 2 and Enable DFE
�@�@Set Charge Pump setting to 5-16 and observe

�@TEST 03
�@�@Adapt Mode = 2, set to Enable DFE
�@�@Set to Enable CTLE Bypass
�@�@TEST 03-00
�@�@�@Enable CTLE Bypass : Set CTLE boost to 0x00
�@�@�@Set Charge Pump setting to 5-16 and observe
�@�@TEST 03-01
�@�@�@Enable CTLE Bypass : Set CTLE boost to 0x01
�@�@�@Observed with Charge Pump set to 5-16
�@�@TEST 03-02
�@�@�@Enable CTLE Bypass : Set CTLE boost to 0x02
�@�@�@Set Charge Pump setting to 5-16
�@�@TEST 03-03
�@�@�@Enable CTLE Bypass : Set CTLE boost to 0x03
�@�@�@Set Charge Pump setting to 5-16 and observe.

�@Also, set VGA_SEL_GAIN of REG 0x84[0] to "1" and set VGA_SEL_GAIN of REG 0x84[0] to "1".
�@Verify the above TEST 01 - 03.

Execution script
// LOG : test_01-03_reg_0x02_CDR_W_20230320.txt
. /25g_retimer_setup_reset.sh
. /25g_retimer_test_xx2_cdr_bandwidth.sh

// test 01V - 03V eq_vga11
// LOG : test_01v-03v_reg_0x02_CDR_W_20230320.txt
. /25g_retimer_setup_reset.sh
. /25g_retimer_test_eq_vga_set2.sh
. /25g_retimer_test_xx2_cdr_bandwidth.sh
# ------------------------------------------------------

# ------------------------------------------------------
# CDR Bandwidth 02
# ------------------------------------------------------
The verification configuration and verification items are the same as those in "CDR Bandwidth 01".
Observed with only the PRBS7 pattern sent from the CPU.

Execution script
// LOG : test_01-03_reg_0x02_CDR_W_PRBS7_20230320.txt
. /25g_retimer_setup_reset.sh
. /25g_retimer_test_xx2_cdr_bandwidth.sh

// test 01V - 03V eq_vga11
// LOG : test_01v-03v_reg_0x02_CDR_W_PRBS7_20230320.txt
. /25g_retimer_setup_reset.sh
. /25g_retimer_test_eq_vga_set2.sh
. /25g_retimer_test_xx2_cdr_bandwidth.sh
# ------------------------------------------------------

Translated with www.DeepL.com/Translator (free version)
    )


    As an additional experiment, we are wondering if it is possible to increase the stability of CDR locking by increasing the CDR bandwidth.

    Is it possible to try several different CDR bandwidth settings and see how they affect the stability of the CDR lock?

    (Answer.)
    ⇒ The verification environment is the same as the following test we have been doing.
    　　CPU --> Retimer --> Retimer
    　　SFP28 --> Retimer --> SFP28
    　　Link training and auto-negotiation are disabled.
    　　No FEC

    　　Observe CDR lock status of CPU --> Retimer
    　　　test_01-03
    　　　test 01V - 03V (with eq_vga = 11)
    　　Add CDR Bandwidth setting to this test.
    　　Attached is the result of observing the CDR lock status.
    　　

    That is all.

    Sorry for repeating, but we would appreciate your verification.

    5504.test_01-03_reg_0x02_CDR_W_20230320.txt2117.test_01-03_reg_0x02_PRBS7_20230320.txt2816.test_01v-03v_reg_0x02_CDR_W_20230320.txt1512.test_01v-03v_reg_0x02_PRBS7_20230320.txt

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Would it be possible to setup a call to discuss this?  I know this has been in debug for a while and I'm wondering if a call might help us resolve the issue more efficiently.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi.

    Sorry for taking so long to contact you.
    We too are in the process of reconfirming the information about the customer's application for the call.
    I asked the customer to measure the CPU --> SFP28 signal, but he replied that it is difficult to confirm.

    They said that if they were to measure the signal, they would have to look at the signal at the input stage of Retimer, but for BGA, they would have to cut the pattern a little far away to look at the waveform, but as they experienced with 10GbE in the past, they could not measure it accurately due to stubs.
    This time, since it is 25GbE, it will be even more difficult.
    They do not have the equipment to measure 25GbE class, so it is difficult to outsource the measurement to a third party due to budget constraints.

    Also, as another question, what do you think about the fact that the CDR with a built-in 25G transceiver is locked when the inside of Retimer is bypassed?

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thanks for working with the customer on this.

    Do they have any channel models and models for their CPU TX?  Perhaps we could try an IBIS-AMI simulation to see if it helps us understand the issue if measurements are not possible.

    Okutsu said:
    Also, as another question, what do you think about the fact that the CDR with a built-in 25G transceiver is locked when the inside of Retimer is bypassed?

    This indicates that something is causing the retimer CDR to fall out of lock, but it's not clear what this is.  Assuming the retimer input has decent signal quality and the data rate matches what the retimer CDR is set to, one of the more common issues is that the input has high jitter.  However, typically, increasing retimer CDR bandwidth can compensate for this.

    Another possibility in some systems is that the retimer cannot lock to the AN signal, but customer said that AN and LT are disabled.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi,

    Thank you for your advice.
    I had a conversation with a customer.

    Regarding the previous question "Do they have any channel models and models for their CPU TX?" the customer ran the simulation and changed the CTLE and DFE values and the EYE pattern improved The customer reported that the EYE pattern improved after changing the CTLE and DFE values.
    As an addendum, he said that the substrate material is megtron6 and that the signal lines are inner-layered.

    I will also change my question about the SFP internal CDR locking up when bypassing the Retimer internals in the 25G transceiver we talked about last time.
    Since the customer is using 25.78125 Gbps, I believe the correct usage is to set it to Enabled in the datasheet.
    Is it appropriate for the IC to be bypassed at this data rate range? Also, are there any concerns?

    One more thing, we are using the default CPU setting of 25Gbps, is it safe to leave the RATE Reg_0x2F[7:4] at the default?
    In what case would you use 6?
    What is the difference from the default?

    I apologize for asking so many questions, but I would appreciate it if you could help me.


  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Apologies for the delay.  Glad to hear that they were able to improve the eye after adjusting CTLE / DFE values.  I think we had recommended using adapt mode 0, where these needed to be manually set.  Are the eye values they get after adjusting CTLE/DFE better than if they use adapt mode 2?

    Since the customer is using 25.78125 Gbps, it is correct to have CDR enabled.  However, this also seems to be the root cause of the problems since CDR lock is being lost.  Typically it would not be necessary to use CDR bypass at this data rate, although this would function fine.

    The causes for CDR lock loss that come to mind are:

    • HEO/VEO threshold not met
    • PPM not good
    • Insufficient transitions

    Yes, for 25G, the default value of 5 should be fine.  You would use case 6 if you wanted the retimer to be able to lock to either a 25.78125 Gbps or 10.3125 Gbps signal.  This is good for systems with compatibility for 10 GbE and 25 GbE.

    Another question I had is whether the customer has measured their reference clock and confirmed that it looks good.  Typically this is not an issue in debug cases I have been involved in, but just an additional thought.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 240 points

    Hi, I'm very sorry for the delay in getting back to you.

    I asked about the customer's response, and it seems that they have another urgent matter to attend to, so we don't know yet what happened after that.
    They are going to check again after May and I will let you know the result then.

    Thanks a lot for your support.

  • 0 in reply to Okutsu
    TI__Mastermind 36043 points

    Hi,

    Thanks for the update, and no problem regarding the delay.  We can continue debugging this when the customer has bandwidth to do so.

    Thanks,

    Drew