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DS90UB948-Q1: AEQ restart

Chuqiang Wen
Expert 5060 points
Part Number: DS90UB948-Q1

Hi Expert, 

We have questions below. Please kindly help check. 

 

Restart AEQ, the EQ(0x3B) status is zero. after running for some time, EQ status suddenly changes to 0x20, then LVDS signal abnormal is detected.

 948 LVDS output is connected to ROHM IC, below errors are detected from ROHM side.

  1. H_TOTAL_MAX_FAIL_H
  2. System fail (LVDS input DE/Clock fail) State， because clock is OK, maybe DE fail

 Even if EQ status changes to 0, LVDS signal abnormal always existed, not recoverable.

948 Lock pin is high level, LVDS clock should be OK.

 Could you help check if the timing of restarting AEQ is right? When issue occurred, 948 output LVDS signal always abnormal, is it possible 948 work abnormally? Because of no such issue without restart AEQ.

 Below is restart AEQ

  1. Restart AEQ by modifying the 948 register:

                0x35=40h

                0x35=00h

  1. Restart AEQ timing

Thanks!

Ethan Wen

  • 0
    TI__Guru** 102905 points

    Ethan,

    Can we back up here - why are you issuing AEQ restart to the 948 in the first place? It looks like you are already applying a digital reset after the 929 init, which will automatically do an AEQ restart. So there is no need to do both 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Expert 5060 points

    Hi Casey,

    Thanks the reply. 

    1.948 digital reset using DIGITAL_RESET1, will AEQ restart do automatically?

    948 register 0x01=01h

    2.Assume both 948 digital reset and restart AEQ are applied, is there any side effects? will cause 948 output abnormal?

    3.If AEQ restart is applied, when EQ changes to 0x20, then 948 output abnormal. But even if EQ changes to 0 automatically, why is the 948 output not recovered? What are the possible reasons for this?

    Regards,

    Ethan Wen

  • 0 in reply to Chuqiang Wen
    TI__Guru* 91340 points

    Hello Ethan,

    Chuqiang Wen said:
    1.948 digital reset using DIGITAL_RESET1, will AEQ restart do automatically?

    Yes, if you perform a digital reset then AEQ will restart.

    Chuqiang Wen said:
    2.Assume both 948 digital reset and restart AEQ are applied, is there any side effects? will cause 948 output abnormal?

    This will not cause output abnormal, but it will force the 948 to unLOCK and reLOCK again which may disrupt the communication between the SER and DES and can result in a fail function if any I2C or GPIO function is affected by that.

    Chuqiang Wen said:
    3.If AEQ restart is applied, when EQ changes to 0x20, then 948 output abnormal. But even if EQ changes to 0 automatically, why is the 948 output not recovered? What are the possible reasons for this?

    If AEQ value is changing during run time, that indicates input signal instability. Please have them use the MAP tool to check the link quality!

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 5060 points

    Hi Hamzeh,

    Actually customer met the black screen issue. Besides adding Restart AEQ, HMI output also changed from Vpp 1300mV to Vpp 800mV. Could you help check if HMI changes are related to this issue? 

    Customer just refer to the 'FPD-Link_DS90Ux929-Q1_Errata-1v6' to do the initialization. May you kindly help review their initialization step for both 929 and 948? Especially help check if any delay needed for each step. 

    929_948 init.txt 
    Step 1: Read state machine status
Reg0x23 = 0x80 //Enable read for the power-up state machine
Reg0x24 = 0x80 //Enable register-read capability of state-machine in register 0x24
Read Reg0x24[4:0] //Read register 0x24[4:0] for power-up state-machine status
If Reg0x24[4:0] has a value of 5’b11011 AND 948 is power on, then go to Step 2

Step 2: Clear registers
• Reg0x24 = 0x00 //Clear register 0x24
• Reg0x23 = 0x00 //Disable read of power-up state machine state

Step 3: 929 init
Reg 0x03=DAh
Reg 0x0E=33h
Reg 0x0F=03h
Reg 0x17=9Eh
Reg 0xC6=0x21

Step 4:929 Init A
Errata #2,#5,#6

Step 5: 929 Init B
Errata #1

Step 6:948 digital reset
Reg 0x01=01h

Step 7: Delay 40ms, then 948 init
Reg 0x1E=55h
Reg 0x1F=05h
Reg 0x41=1Fh
Reg 0x49=E0h
Reg 0x05=9Eh
Reg 0x26=1Bh
Reg 0x27=17h

Step 8: Delay 30ms then Restart AEQ
Reg 0x35=40h
Reg 0x35=00h

Step 9: Clear 929 INT flag
Read Reg 0xC7

Step 10: Clear link lost flag
Reg 0x04=A0h
Reg 0x04=80h

    Thanks!

    Ethan Wen

  • 0 in reply to Chuqiang Wen
    TI__Guru* 91340 points

    Hello Ethan,

    I have modified the used script. However, AEQ reset is not needed at this point!

    Additionally, can you provide register dumps from the 929 and the 948 at the time of black screen?!

    1) First you need to make sure you are fulfilling the power-up sequence as per datasheet.
2) After PDB is high, you have to implement a 2ms delay before making any I2C transaction into the 929.
3) At this point you can write the followings:

Step 1: 929 init
Reg 0x03=DAh
Reg 0x0E=33h
Reg 0x0F=03h
Reg 0x17=9Eh
Reg 0xC6=0x21

Step 2:929 Init A
Errata #2,#5,#6

Step 3: Wait for stable HDMI CLK. HDMI Clock must be within 0.5% of the target frequency and stable for at least 1uS.

Step 4: Read state machine status
Reg0x23 = 0x80 //Enable read for the power-up state machine
Reg0x24 = 0x80 //Enable register-read capability of state-machine in register 0x24
Read Reg0x24[4:0] //Read register 0x24[4:0] for power-up state-machine status
If Reg0x24[4:0] has a value of 5’b11011 AND 948 is power on, then go to Step 5

Step 5: Clear registers
• Reg0x24 = 0x00 //Clear register 0x24
• Reg0x23 = 0x00 //Disable read of power-up state machine state

Step 6: 929 Init B
Errata #1

Step 7:948 digital reset
Reg 0x01=01h

Step 8: Delay 40ms, then 948 init
Reg 0x1E=55h
Reg 0x1F=05h
Reg 0x41=1Fh
Reg 0x49=E0h


Step 8: Delay 30ms then Restart AEQ
Reg 0x35=40h
Reg 0x35=00h

Step 9: Clear 929 INT flag
Read Reg 0xC7

Step 10: Clear link lost flag
Reg 0x04=A0h
Reg 0x04=80h