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DP83TC812R-Q1: DP83TC812x - handling of link control

Paul Fleischmann
Prodigy 10 points
Part Number: DP83TC812R-Q1
Other Parts Discussed in Thread: DP83TC811, DP83TC812S-Q1

In the SNLS579A document for DP83TC811, register 0x485 bit 12 is link control bit, but in the SNLA293

for both master and slave configuration register 0x475 bit 4 is used for link control.

 

1) When the the device is initialized, is bit 12 in register 0x485 enough for setting the link control?

2) For DP83TC812 only bit in SNLA389A Open Alliance document (register x0523, bit 0) is mentioned, is

   for handling link control this bit enough or is there another bit, like bit 12 register 0x485 for DP83TC811,

   which is not documented in SNLS document?  

3) Is the link control handling of DP83TC812 similar to DP83TC811  or is disabling/ enableingt of he link control for DP83TC812 not supported in hw

  • 0
    TI__Expert 8650 points

    Hi Paul,

    Paul Fleischmann said:
    1) When the the device is initialized, is bit 12 in register 0x485 enough for setting the link control?

    No, please follow the configuration mentioned in the SNLA293 app note, 0x475 also has to be written which cuts down the Transmitter for Link Control.

    Paul Fleischmann said:

    2) For DP83TC812 only bit in SNLA389A Open Alliance document (register x0523, bit 0) is mentioned, is

       for handling link control this bit enough or is there another bit, like bit 12 register 0x485 for DP83TC811,

       which is not documented in SNLS document?  

    The procedure following in the Open Alliance appnote for DP83TC812 is correct, you can follow that method.

    Paul Fleischmann said:
    3) Is the link control handling of DP83TC812 similar to DP83TC811  or is disabling/ enableingt of he link control for DP83TC812 not supported in hw

    Both they PHYs function differently, I would recommend following the register writes mentioned in each of their respective Open Alliance application notes.

    Thanks,
    Rahul

  • 0 in reply to Rahul
    Prodigy 10 points

    Hi Rahul

    ok i am little bit confused cause there are several different information about link control handling in following 3 3 documents www.ti.com/.../dp83tc812s-q1 , www.ti.com/.../snla389 and www.ti.com/.../snla404 related to dp83tc812.

    From snla389a.pdf

    and

    From dp83tc812s-q1  it is mentioned that register 0x1834 is except bit 14 all other bits are from type R which means only readable but from snla389a.pdf some only readable bist shall be set.

    And in snla404.pdf , appendix A there is a flow chart describing the initialization sequence and it mentions about Enable link start-up and Disable link start-up but no "real" information available which registers needs to be set to Enable link start-up and Disable link start-up.

    Which registers needs to be set and which value must be set to Enable link start-up and Disable link start-up?

  • 0 in reply to Rahul
    Prodigy 10 points

    Hi Rahul

    ok i am little bit confused cause there are several different information about link control handling in following 3 3 documents www.ti.com/.../dp83tc812s-q1 , www.ti.com/.../snla389 and www.ti.com/.../snla404 related to dp83tc812.

    From snla389a.pdf

    and

    From dp83tc812s-q1  it is mentioned that register 0x1834 is except bit 14 all other bits are from type R which means only readable but from snla389a.pdf some only readable bist shall be set.

    And in snla404.pdf , appendix A there is a flow chart describing the initialization sequence and it mentions about Enable link start-up and Disable link start-up but no "real" information available which registers needs to be set to Enable link start-up and Disable link start-up.

    Which registers needs to be set and which value must be set to Enable link start-up and Disable link start-up?

  • 0 in reply to Paul Fleischmann
    TI__Expert 8650 points

    Hi Paul,

    Apologies for the confusion caused in the documentation.

    Reg 0x1834 is configured only for the master and slave configuration of the PHY.

    The description of Step-1 should actually be added in the Step-2 for section 7.1, writing to reg 0x0523h should disable the transmit.

    I will make sure to document this and correct in the future revisions of the datasheet.

    Thanks,
    Rahul