[Question #1]
The OVERCUR*Z pins are (usually) inputs from a USB load switch that indicates OC conditions via a FAULT pin.
Do the OVERCUR*Z pins include an internal PU?
The Pin Functions table in the DS seems to indicate "yes".
If so, what is this resistance?
100kΩ±20% or something?
Better yet, do all the control-logic I/O pins share similar PU/PD values?
If so, what are they?
[Question #2]
In a particular application, some of the downstream ports will not need power control (no USB load switch control), others will.
Is my below understanding correct?
1) FULLPWRMGMTz/ SMBA1/SS_UP = Floating (Internal PD will set operation to allow external power path control for DS ports)
2) PWRCTL_POL = Floating (Interal PU will set operation to use active-high logic)
3) GANGED/SMBA2/ HS_UP = Floating (Internal PD will set operation to use individual port power management (pwrctl[4:1] for each channel)
4.1) PWRCTL*/BATEN* = Floating (Internal PD disables load switch control) OR
4.2) PWRCTL*/BATEN* = external PU (external 4.7kΩ resistor recommended to PU, which enables load switch control for that channel)
5) OVERCUR*Z = Floating (Internal PU = No Overcurrent Condition; Load Switch pulls signal H/L via Open-Drain) Datasheet however recommends external 10kΩ PU resistor - see Figure 10 in the DS)
Following-up on OVERCUR*Z...what is the pin's input resistance, and the PU resistance?
If input resistance was 100kΩ and PU resistance was say 47kΩ, then I see how a voltage divider affect would cause the input voltage (V_IH) to only be ~2.2V or so.
Having that external 10kΩ would keep the parallel PU resistance around 8k, and then V_IH would be ~3V.
Am I understanding why this external PU is recommended?
Regards,
Darren
