Hi,
I want to use the SNx5DPHY440SS as a CSI retimer on an interface board in between two connectors
To facilitate the layout and have cleaner traces i would like to connect the DPHY in the following way :
To sum up :
connector 1 | DPHY440 | connector 2
¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬
D0N | DA/B0 P | D0N
D0P | DA/B0 N | D0P
D2N | DA/B1 P | D2N
D2P | DA/B1 N | D2P
CLK P | CLK P | CLK P
CLK N | CLK N | CLK N
D3N | DA/B2 P | D3N
D3P | DA/B2 N | D3P
D1P | DA/B3 P | D1P
D1N | DA/B3 N | D1N
From the datasheet and other questions on the forum, it seems that plugging any lane number anywhere on the DPHY440 is fine if the lane number are kept identical on the camera and CPU in a CSI application
The datasheet states that the DPHY440 doesn't support inverting polarity on the data lanes but if lanes are inverted on both sides of the DPHY, does it works ?
Do we need to invert all the lanes for this to work ? As in my schematic, the clock and the channel 3 are not inverted
Also, it seems from other posts in the forum that for the DPHY to work in the CSI 4 lane configuration, it needs some i2c commands to be send, is it so ?
( From other posts on that forum :
Write Register 0x50 with 8’h01 //Override enable for HS TX path
Write Register 0x51 with 8’h01 //HS TX path enabled.
Write Register 0x61 with 8’h00 // Disable LP path.
Write Register 0x70 with 8’h01 //Override enable for HS RX path
Write Register 0x71 with 8’h01 // HS RX path enabled.
Bit 0 is lane 0
)
Thanks a lot in advance,
Sylvain
