SN65LVDS33D Interpair and intrapair skew

Muni Pavan Kumar Reddy Kona

Hello,

I am looking for inter pair skew details of SN65LVDS33D.

To clarify, I am looking for delay variation at outputs between 1Y,2Y,3Y and 4Y.

Let us assume I gave same clock input differentially at inputs 1A, 1B and 2A,2B what is delay variation at 1Y and 2Y in nsec.

Thanks,

Muni

over 2 years ago

0 Joshua Salinas over 2 years ago

TI__Mastermind 22400 points

Hello Muni,

Inter/Intra pair skew are not typical specs for LVDS devices. It's more PCB routing than device that contribute to increase skew. Page 4 of SNLA302 has layout guidelines to minimize skew.

Regards,

Josh

0 Muni Pavan Kumar Reddy Kona over 2 years ago in reply to Joshua Salinas

Prodigy 250 points

Hello Josh,

Thank you for your reply. I will take care in the routing. I want to allocate some budget for the device itself since i have a strict requirement that all the signals should reach with in 5ns of time.

0 Joshua Salinas over 2 years ago in reply to Muni Pavan Kumar Reddy Kona

TI__Mastermind 22400 points

Hello Muni,

No problem. Let's us know if there is additional assistance.

Regards,

Josh

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SN65LVDS33D Interpair and intrapair skew