DS90UB941AS-Q1: random unlock issue

Ryan Wang

Expert 7700 points

Part Number: DS90UB941AS-Q1

Dear expert,

Customer already mass production for over 100Ku UB941 with no problem.

Now they met random unlock issue with 3 pcs UB941 with UB948.

UB941 use external 133M clock and shows problem.

The problem is gone if using DSI clock or internal clock.

It seems problem comes from external clock.

But ABA swap experiments is done. the phenomenon goes with UB941 silicon.

External clock is very stable with scope measurement.

Customer doubt the problem comes from UB941 internal circuit after external clock come in. Do you have any comment on this?

Thanks

over 3 years ago

0 Shu Huang over 3 years ago

TI__Mastermind 18046 points

Hi Ryan,

Can you share the configuration and initialization sequence when in external clock mode? Is it continuous or discontinuous mode and what is the sequence of the clock relative to the power up sequence?

Best,

Shu

0 Ryan Wang over 3 years ago in reply to Shu Huang

TI__Expert 7700 points

Shu,

Here you areUB941, UB948 all register dump for both good and bad case.

It is continuous mode.

I am asking customer to check power up sequence of clock. Will feedback you soon.

941 948 register.xlsx

0 Shu Huang over 3 years ago in reply to Ryan Wang

TI__Mastermind 18046 points

Hi Ryan,

Thanks for the information. I will need time to review the registers in addition to the power up sequence once provided. I plan on providing an update by the end of this week 1/20.

Best,

Shu

0 Ryan Wang over 3 years ago in reply to Shu Huang

TI__Expert 7700 points

Shu,

"Reference clock frequency stability +-100 PPM

Reference clock jitter , fPCLK / 40 < Jitter frequency < fPCLK / 20, TJ@BER<1E-10, Max 0.28 UI

SSC Tolerance: up to 33 kHz modulation at 25 MHz - 210 MHz"

Above is from UB941 datasheet, how to understand all this requirement?

Does it mean UB941 can tolerate +-33KHz clock jitter?

For example PCLK=100MHz, " fPCLK / 40 < Jitter frequency < fPCLK / 20" mean 2.5MHz<Jitter<5MHz? What does it mean?

For example PCLK=100MHz, UI is 5ns, right? 0.28UI=1.4ns, 10ns clock duration can become 10+/-2*1.4ns, right? which translate to 78MHz to 139MHz? So high range?

"Reference clock frequency stability +-100 PPM" And does this frequency stability mean jitter as well? Or frequency is not accurate with some offset but it is still stable?

What relationship between this 100ppm and 0.28UI and fPCLK / 40 < Jitter frequency < fPCLK / 20?

I want to let customer check whether their oscillator meet our requirment.

Thanks

0 Shu Huang over 3 years ago in reply to Ryan Wang

TI__Mastermind 18046 points

Hi Ryan,

The clock frequency stability (PPM) and jitter frequency (UI) are not related. The PPM is the accuracy of the external clock source, where as jitter is how the clock propagates throughout the system.

You can find the reference clock frequency stability in the oscillator datasheet. Jitter, you would have to measure from the system and compare to the 0.28UI that we have defined.

Please refer to the 941 REFCLK Jitter FAQ and walk the customer through that process as this is also something we need to verify.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1050269/faq-ds90ub941as-q1-dsi-or-refclk-jitter-measurement?tisearch=e2e-sitesearch&keymatch=ds90u%2525252525252525252A94%2525252525252525252A%25252525252525252520OR%25252525252525252520ds90u%2525252525252525252A98%2525252525252525252A

As for SSC tolerance, this is also separate from jitter and a different feature all together. Do you know if customer has a spread spectrum clocking input? The requirement will only be applicable if there is an SSC input.

Best,

Shu

0 Ryan Wang over 3 years ago in reply to Shu Huang

TI__Expert 7700 points

Shu,

Customer didn't use SSC.

Great thanks

0 Ryan Wang over 2 years ago in reply to Ryan Wang

TI__Expert 7700 points

Shu,

Customer take some measurement for this issue. Need your guidance here. Thanks

Below is their 133MHz clock. 26PPM which should be good, right?

Below is their power up sequence which looks also fine.

0 Shu Huang over 2 years ago in reply to Ryan Wang

TI__Mastermind 18046 points

Hi Ryan,

The 26 PPM is fine. I need to brainstorm with the team. Can you share more details on how it is unlocking?

I would also like additional register dumps of the indirect DSI pages

Can I also have the layout and schematic? You can email them to me.

Best,

Shu

0 Ryan Wang over 2 years ago in reply to Shu Huang

TI__Expert 7700 points

Shu,

Customer wants to send us for ATE test. Is it OK?

Below is their sch, PCB and LOCK.

LOCK: 1s/div

0 Shu Huang over 2 years ago in reply to Ryan Wang

TI__Mastermind 18046 points

Hi Ryan,

I want to double check the indirect DSI registers too before we proceed to ATE. Can you share those?

Best,

Shu

0 Ryan Wang over 2 years ago in reply to Shu Huang

TI__Expert 7700 points

Shu,

I'm a little confused.

This is FPDlink random unlock issue. And the issue only happen with their external clock (3pcs among 300Kpcs). The problem won't happen with either DSI clock or UB981 internal clock.

Why you want to check indirect DSI registers?

And besides finding root cause for this issue, customer more care about how to screen this kind of silicon in their production line.

Below is register dump for both good and bad UB941.

Before unlock, I didn't find any key difference between good one and bad one. Even for CRC (0xA, 0xB registers)

Do we have some other reserved registers to check?

4606.941 948 register.xlsx

0 Ryan Wang over 2 years ago in reply to Ryan Wang

TI__Expert 7700 points

Shu,

Is it possible to run BIST from UB941 side to screen the failure silicon?

Customer only has SoC at UB941 side. Can this SoC launch BIST and then check BIST result which is at UB948 side?

1. Can BIST_EN in below register enable BIST from UB941 side? Don't need to configure UB948 for BIST , right? What does DOPL_MODE mean?

TX_BIST_CTL Register (Address = 0x14)

2. SoC can check below UB941 register for BIST BC err. But for FC err, it has to read UB948 BIST err register, right? But in BIST mode, can SoC at UB941 side read UB948 register?

BIST_BC_ERRORS Register (Address = 0x1B)

3. What does PATGEN_BIST_ERRS this register mean? PGBE Register (Offset = 0x19)

0 Hamzeh Jaradat over 2 years ago in reply to Ryan Wang

TI__Guru** 112840 points

Hello Ryan,

Shu is OoO and will be back in two days!

0 Shu Huang over 2 years ago in reply to Ryan Wang

TI__Mastermind 18046 points

Hi Ryan,

1. BIST can only be run on the deserializer side and the I2C need to be configured like below:

DOPL means Dynamic Operation Life. It's another test mode used during reliability testing, unrelated to BIST. DOPL mode ensures that a large portion of the device is toggling.

2. Remote I2C is unavailable in BIST mode so everything will need to be accessed directly, including deserializer register 0x25 on the 948 for the BIST errors.

3. Since BIST mode on the 941AS does not actually output video, the PATGEN_BIST_EN bit on 948 is an alternative form of BIST/PATGEN that does output video. PATGEN_BIST_ERR is monitored at 948 to observe/count errors.

0 Ryan Wang over 2 years ago in reply to Shu Huang

TI__Expert 7700 points

Shu,

Great thanks for your detailed feedback. I will send 2 silicon for ATE.

If you have more advice , pls let me know.

0 Shu Huang over 2 years ago in reply to Ryan Wang

TI__Mastermind 18046 points

Hi Ryan,

Sounds good, I will be on standby if you have further questions.

Best,

Shu

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DS90UB941AS-Q1: random unlock issue