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DS90UB948-Q1: Customer support - Maximum pixel clock design question

Henry Chan
Prodigy 600 points
Part Number: DS90UB948-Q1

Hi Team, 

Our customer is interested in designing with our DS90UB948-Q1 using 96Mhz pixel clock in single channel.

 Can you help or pass below questions:

  1. Please advise if we recommend to design with 96Mhz pixel clock, which is capped for DS90UB948-Q1.
  2. Please provide some design tips for such design, is there anything to be aware of.

 Thank you very much!

Thanks

  • 0
    TI__Guru** 103215 points

    Hello Henry,

    96MHz is supported by 948 in single link mode, and that is a spec which we can guarantee the device for. When operating at high single link speeds, please take care to ensure that the channel s-parameters between the SER/DES can meet the FPD-Link channel specifications (contact TI internally or under NDA). At higher link speeds, this may mean that the cable length needs to be reduced to meet the allowable loss budget up to the channel frequency depending on the type of cable which is used. Also make sure that the serializer selected can support 96MHz in single link mode, and make sure that the input source to the serializer can meet the allowable PCLK jitter requirements in the SER datasheet. 

    If needed, our team is happy to help review design implementation such as schematics and layout to ensure better first time success. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Prodigy 600 points

    Hi Casey,

    Thanks for the help.

    What about using 2 48MHz single link? which add up to 96MHz, as it is really close to the limit, if we slightly exceed the 96MHz, will there be any issue?

  • 0 in reply to Henry Chan
    TI__Guru** 103215 points

    Hello Henry,

    In dual link mode, 96MHz per FPD channel is also supported, so 48MHz per channel is no issue. 

    Best Regards,

    Casey