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PCA9555: I2C SDA/SCL undershoot impact

Part Number: PCA9555

Hi,

Customer reported I2C SDA/SCL undershoot found with PCA9555. Please see customer description below and help to comment.

 

Need your support to clarify the observation in using TI PCA9555APW. 

We found the I2C clock sent from FPGA to the PCA9555APW, the clock signal accompanied by a huge undershoot signal. The operation voltage is 3.3V but the undershoot looks like around 0.8V~0.9V.

Will it impact the PCA9555 decoding of the I2C signal or IC reliability? What is the requirement/specification to undershoot, the I2C-related signal? Can you help to identify the spec. and design guidance?

Best regards,

Randy

  • Ensure that this is not a measurement artifact; use a ground spring instead of a ground clip with the oscillosope probe.

    The absolute maximum ratings forbid less than −0.5 V if the current is not limited to 20 mA. I do not know if this current is reached in this situation. I'd estimate that this is harmless.

    Try to reduce the drive strength of the FPGA pin, or add a small source termination resistor.

  • Hi Randy,

    Clemens has provided some very good points to look into here. 

    Please make sure this isn't from a artifact in your measurement setup. The GND spring that Clemens is referring to looks something like this:

    The purpose is to cut down on the GND loop formed by the long cable GND usually present on the o-scope probe. The GND spring allows for a more accurate measurement due to less inductance in the cable. The more inductance, the more that we will see 2nd order overshoot (like you see in your scope captures) due to quickly changing voltages. 

    Here are the absolute maximum ratings that need to be respected in order to guarantee that the device will not be potentially damaged during operation. I suspect the same as Clemens that this voltage undershoot is probably harmless due to the unlikely scenario that these undershoots are reach +/- 20mA current range, but still we need respect these abs. max ratings at all times. 

    When you have series inductance (inductance from wire / pcb trace) and a shunt capacitance (input/output capacitance / parasitic capacitance) you effectively have a resonant circuit. Driving a fast rising/falling signal will cause this circuit to resonant. Best practice is to add a damping resistor between source and load to help reduce the undershoot you are seeing per Clemens's suggestion.

    Regards,

    Tyler