DP83822H: TXCLK and RXCLK Frequency Issue in DP83822HRHBR

Hi Team, We are using the ‘DP83822HRHBR’ Phy chip which is interfaced with MPC5777C controller. The Phy Link is not up. We tried setting the Phy to 100MBPS in Full Duplex Mode.

We checked the frequency for the signals and the below table has the findings: Signal Name Reading (Oscilloscope) Remarks RX_CLK 12.5MHz For 100 Mbps it should be 25MHz as per the Phy data sheet and 2.5MHz for 10 MBPS speed. Note: We are reading 1.25 MHz when we configure the PHY to 10Mbps FEC_MDC 2.5MHz TX_CLK 12.5MHz For 100 Mbps it should be 25MHz as per the Phy data sheet and 2.5MHz for 10 MBPS speed. Note: We are reading 1.25 MHz when we configure the PHY to 10Mbps XI 25 MHz

The ‘RX_CLK’ and ‘TX_CLK’ are set to 12.5MHz which is half of 25 MHz which is the correct frequency for 100MBPS. We see ‘RX_CLK’ and ‘TX_CLK’ are set to 1.25MHz with 10Mbps configuration which is again half of 2.5MHz. The input clock is fed to ‘XI’ pin which is 25MHz. Below is the Phy Dump of a few of the registers for 100MBPS,