TL28L92: Time-out and RTS issues

Arnaud,

An engineer has been notified of this thread and will respond by end of business 01/26/2023 CST.

Regards,

Eric Hackett 

Hi Arnaud,

I've reached out to a digital design engineer to see if he can look at the internal logic of the device to verify case #1 and #2 and also see if there is any additional actions required to enable RTS on case #3.

I suspect it may take a few days for him to get back to me. I'll ping him again on Tuesday of next week if I don't hear back from him.

-Bobby

Hi Bobby,

Thank you very much for your feedback!

Looking forward to hearing from you soon.

Regards,

Hi Arnaud,

The design engineer got back to me with some details about case #1, for case number 2 he seemed to only give me the logic for setting the trigger levels without telling me what they actually are. No comment to number 3 yet... 

I'll press to see if I can get more details.

-Bobby

---------------------------

#1)

For the timer_int_en net internal to the device, (acr[6:4]==3'b100) || (acr[6:4]==3'b101) || (acr[6:4]==3'b110) || (acr[6:4]==3'b111)

It seems like this portion of the logic is what we expect it to be. 

Is it possible that there isn't a long enough wait time to set off the interrupt?

#2

assign rx_trigger_level_a       = {mra_0[6],mra_1[6]};

assign tx_trigger_level_a             = {mra_0[5],mra_0[4]};

Hi Bobby,

#1)

For testing purposes, I send only one frame of 8 bytes to the UART. Therefore, there is enough wait time after the 8th byte the set off the interrupt.

The time-out is set to 2 characters time and I also tried with 10 characters time.

ACR[6:4] = 3'b001. That's what I used with SCC2691 and SC28L91 but it seems like it's not supported anymore.

Trace 1 is the pin 29 RxDA. Trace 2 is the pin 18 INTRN.

You can see 8 interrupts (1 / character) but the interrupt "Counter Ready" at the end of the frame is missing.

ACR[6:4] = 3'b011 or ACR[6:4] = 3'b111

You can see 8 interrupts (1 / character) + the interrupt "Counter Ready" after two characters time.

I consider this point as solved.

#2)

I checked again and the table 3-23 seems not to be correct. Note that the datasheet indicates bits MR0[6] and MR1[6] instead of MR0[4] and MR0[5].

What we expect by reading the datasheet (FIFO = 16 bytes):

The real behaviour is as follows. I have tested the four combinaisons.

I consider this point as solved too but the datasheet should be updated.

#3) 

That's the most important issue to me because I need the RTS working in my design.

Regards,

Hi Armaud,

Thanks for the additional information on cases #1 and #2.

For case #3:
I asked how to enable the RTS logic within the device which I am told is 

MR1A bit 7 = 0

MR2A bit 5 = 1

CRA bits [7:4] = 4’h8 

Are you able to do a register read of these to verify the data written is correct?

-Bobby

Hi Bobby,

Thank you for your answer.

Here is what I read:

MR1A = 0x13 → bit 7 = 0

MR2A = 0x27 → bit 5 = 1

Not sure that I can read the register CRA? Address 2 is reserved. When I try to read the address 2, I always get 0x0F.

Regards,

Hey Arnaud,

This device is quite old in our portfolio and until recently we haven't had too many questions on this (my guess is with the competitor's obsolete device people are flocking over to use ours). We currently don't have an EVM (evaluation module) for this device. I'm going to talk to my manager to see if we can get the go ahead to make one and try to recreate your issue. I suspect though this may take quite a bit of time (maybe 2 months?). Is this issue your having something that can wait that long to try to address? 

-Bobby

Hi Bobby,

I fully understand that this device is quite old but I don't know if we can wait that long because this UART is a part of an "old" design that we must maintain for our customers.

I'll talk to my manager too and I will do some extra tests. I shall keep you updated.

Regards,

Hi Arnaud,

Just a heads up, my manager did approve for our team to move forward with making an EVM and trying to validate the current datasheet as much as we can. If it's still within your timeline, we will try to replicate and find a workaround with your case #3 once the EVM has been designed, fabricated, and delivered to us.

My current expectation is ~2 months to design and receive EVMs and then a week or 2 to get a set up (code as well) working.

I suspect we you to provide your UART initialization code (what registers to write to  and the data you write into them when you power up, preferably pseudo-code or a simple step1: write 0x23h into register CRA, step 2 write 0x44h into register CSRA ect.)

-Bobby

Hi Bobby,

Sorry for the delay in responding I was out of the office.

That sounds good! I talked with my manager and we can wait 3 months on this project. Of course, we can provide a pseudo-code.

I tried again but I haven't been able to assert the RTS.

Thank you we appreciate your cooperation!

Regards,

Hi Arnaud,

Thanks for the reply. 

My colleague is currently working on the PCB. Our current status:

We've submitted a model request (for the TL28L92 device) to a third party company to have it created for our PCB designer tool.

I suspect the model should be completed by mid next week. Afterwards my colleague will begin the schematic process.

I'll try to give you an update as things progress.

-Bobby

Hi Bobby,

Thank you for your feedback.

In the meantime, I fount out a solution for the RTS! I must set the output 0 (OP0 = RTS) by writing 0x01 in the register SOPR. Then, the UART automatically reset the output at the end of the emission.

But the command 0b1000 "Assert RTSN" in CRA definitively does not work...

Of course, I remain at your disposal should you have any requests for your EVM ;-)

Regards,

Arnaud,

We will respond to this thread once we have an update. Thanks for the follow up.

Regards,

Eric Hackett