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SN65LVDS100: Is datasheet figure 48 correct?

Part Number: SN65LVDS100

In the Datasheet, figure 48 shows a Vcc/2 bias for a cmos input.

Will this also work for the SN65LVDT device with the built in termination?  

The absolute range Vid says 1V.  Does this Vid of 1V apply to both devices with or without built in termination? 

Or does the one without built in termination can go way past Vid of 1V like figure 48 shows? 

Also, can this setup also reach 2Gbps as well?  The table below the diagram mentions 500mbps.

Thanks.