DP83849I: Regarding to PWRDOWN pin

Masakazu Adachi

Part Number: DP83849I

Hello team,

I received a question from the customer.

Is the only way to stop the output of the SLP signal, etc., by controlling the RESET signal?

The customer's situation is as follows,
During normal use, the device is operated with PWRDOWN_INT = High, but the register setting value is to be used as it is, so the customer wanted to control PWRDOWN_INT = Low instead of RESET control, so that no waveforms are output to the Ethernet pin. However, when the auto-negotiation function is turned off, even if PWRDOWN_INT = Low, the SLP signal is output and the link up/down is repeated. So, is the only way to prevent the SLP signal from being output, etc., by controlling the RESET signal?

Regards,

Masa

over 2 years ago

0 Gerome Cacho over 2 years ago

TI__Mastermind 39775 points

Hi Masa,

I am unfamiliar with terminology of SLP. Do you mean the MDI or MII signals? Keep in note that DP83849 is a duel PHY, so could it be possible that you are observing on PHY A portion while pulling down PHY B's PWRDOWN_INT or vise versa?

From what I am understanding, you are asking if MDI or MII signals are dead when a PHY's PWRDOWN_INT are held low correct?

Sincerely,

Gerome

0 naotoku okamura over 2 years ago in reply to Gerome Cacho

Prodigy 30 points

Sorry my question was about the FLP signal and NLP signal, not the SLP signal.

I want to completely stop communication without initializing register settings.

Does controlling PWRDOWN_INT to Low stop not only data communication but also link communication? (Will the signal output stop?) Or does it not stop unless RESET is controlled?

Best Regards,

Okamura

0 Gerome Cacho over 2 years ago in reply to naotoku okamura

TI__Mastermind 39775 points

Hi Okamura,

Please allow me to discuss with the team. I will reply in the next 2 days.

Sincerely,

Gerome

0 Gerome Cacho over 2 years ago in reply to Gerome Cacho

TI__Mastermind 39775 points

Hi Okamura,

Please see section 6.2.4.1 of DP83849 datasheet. Per section, the register block will be the only portion active with rest of the portions of PHY not active. This is the expected behavior. Please relay and have customer check this out.

Sincerely,

Gerome

0 naotoku okamura over 2 years ago in reply to Gerome Cacho

Prodigy 30 points

I confirmed that send of the FLP and NLP signal was stopped by the PWRDOWN_INT pin. However, when I refer to LINK STATUS register, it repeats link-up and link-down. Is the DP83849 receiving signal?

Best Regards,

Okamura

0 Gerome Cacho over 2 years ago in reply to naotoku okamura

TI__Mastermind 39775 points

Hi Okamura,

Could you please expand upon your statement:

naotoku okamura said:
However, when I refer to LINK STATUS register, it repeats link-up and link-down.

It may be best to provide a register dump of 0x1.

Sincerely,

Gerome

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DP83849I: Regarding to PWRDOWN pin