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DP83867CR: In dual PHY system, one phy is not going to 1Gbps

Part Number: DP83867CR

Hi,

I have dual PHY ic connected to zynq processor. Both sections are same in both hardware and software aspect. I am able to ping only one PHY but not the second PHY

Both links are up. But second PHY speed is limited to 100Mbps. (PHY 2 is being detected by processor by reading 0xa231 in reg 3)

1. I have tried with same ethernet cable and same link partner as that of PHY 1. 

2. I have given software reset by writing to 0x1000 to 0x001f

3. I have tried by disabling 10mbps and 100Mbps to force 1Gbps speed (this was there in some answer in the forum).

4. I have tried by writing 1 to 9th bit of 0x0009 reg(. Configuration Register 1)

Please help

Regadrs,

SCH

  • Hello,

    What MAC interface is being used for both PHYs? Have you tried using loopback testing to understand where the data is getting lost? Is both PHYs intended to be at 1G, or is second PHY at 100mbps unintended?

    Sincerely,

    Gerome

  • Hi Gerome,

    Thanks for the reply. Both are supposed to work at1Gbps. Tried loopback as well. In the booting process the speed shows to be 1Gbps but in 2sec link becomes down. No data will be sent. Its happening in only second PHY. I have also compared the registers of both PHY s. It says link Partner does not desire Next Page Transfer. But i am using the same PC and cable which I use to create link with PHY 1. 

    Regards,

    SCH

  • Hello,

    On both PHYs, can you please share registers 0x1, 0x6E, 0x6F, 0x4, 0x9, 0xA, 0x11 when they are each connected to the cable?

    Sincerely,

    Gerome

  • Hi Gerome,

    Sorry for the delay in response. Board got crashed while testing. Now i am able to read the data. In both IC s 6E and 6F register i am getting 0XA8 and 0X3000 respectively

    Best Regards

  • Hello,

    I see that auto-negotiation has been disabled via strap (0x6E[7]). We strongly do not recommend this setting especially if 1G speeds are desired. Please try enabling auto-negotiation either via registers and soft resetting (0x1F[14]) or power cycle with RX_CTRL strapped into mode 3.

    Sincerely,

    Gerome