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SN65DSI86-Q1: DSI LANE error 0xF6-Bit6

Shinji Mada
Prodigy 136 points
Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: SN65DSI86, TEST2

Hi, TI.

I use SN65DSI86 in MIPI DSI receiver, and TC358778(TOSHIBA) in RGB-DSI converter.
My system has the TC358778 receiving RGB data and passing it to the SN65DSI86 using the MIPI DSI lane.

When using DSI LANE x1 in low data rate, error bit in 0xF0-F8 are all 0. It's good.
But, when using DSI LANE x2 or x4 in high data rate, an error appeared in register 0xF6 Bit6 (LOSS_OF_DP_SYNC_LOCK_ERR).

I tried lane swap and polarity reversal, but it didn't work.

Can you guess what's wrong?


Thank you.

  • 0
    TI__Genius 13310 points

    Hello,

    Address 0xF6 report errors associated with DSI to DP video timing. Typically, errors are set in these registers when video timing programmed into DSI86 doesn’t match timing received on the DSI interface. It is important the DSI86’s video registers located from 0x20 thru 0x3A match video timing used by the DSI source. The DSI86 will derive the DP timings from values programmed into these registers.

    What data rates are you toggling between?

    Are you configuring your DSI86 registers between the three different configurations?

    How are you configuring your registers? If not already using, please use https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers.

    Thanks,

    Zach

  • 0 in reply to Zach Dryer
    Prodigy 136 points

    Hello, thank you for reply quickly.

    And, solved the problem.
    It was caused by a difference in settings.

    One more question.
    Is there a register (like a counter) that can confirm that the DP lane is passing the video stream successfully?

  • 0 in reply to Shinji Mada
    TI__Genius 13310 points

    Hello, 

    There is not a counter. However, you can see which  lanes are enabled by register 0x10. You can all check for any errors in F0 - F8 register for errors with timing synchronization, issues with the DSI MIPI side, failure for DP to link train etc. You can also plug the system into a display to confirm whether the video stream is being passed successfully.

    Thanks,

    Zach

  • 0 in reply to Zach Dryer
    Prodigy 136 points

    Hello. Thank you information, I understood to check 0xF0-F8 register.

    SN65DSI86 output is connected to the DP receiver device, not display panel.
    Error register in 0xF0-F8 are all clear, and c    ompleted DP training and linked up, but,  DP receiver doesn't recognize MSA.

    Register 0x20-0x3A are set correctly for the video data stream. (refer to 8.4.4.6 in datasheet)

    I tried 3 different settings below in 8bit mode with the same result.

      0x56 = 0x20 , 0x57 = 0x00  (RGB unspecified color space)

      0x56 = 0x28 , 0x57 = 0x00  (CEA RGB)

      0x56 = 0x38 , 0x57 = 0x00  (Adobe RGB)

    Are there any other settings needed?

  • +1 in reply to Shinji Mada
    TI__Genius 13310 points

    Hello,Shinji,

    How are you configuring the device? 

    Please use the excel sheet in this link to configure the device:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers 

    Also check if the receiver device has ASSR capability or not?

    Thanks,

    Zach

  • 0 in reply to Zach Dryer
    Prodigy 136 points

    Hello, thank you for your help.

    As you pointed out, the receiver device did not support ASSR.

    Setting it to no ASSR worked fine.

    And more question.

    Is there a wait time required by the I2C interface?

     For example, after EN=1.... After the PLL has locked.....  Before and after the DP lane links.....

    In my system, FPGA settings SN65DSI86 by I2C interface.

    When EN=1, the FPGA will continue to write until it finishes setting. (no read operaton.)

    The write access interval is 10ms, but most of the time the DP lane training fails. It can be successful sometimes.

    Writing it manually works fine 100%, so I doubt a timing constraint.

    Thanks.

  • 0 in reply to Shinji Mada
    TI__Genius 13310 points

    Hello, Shinji,

    Did you make sure that TEST2 pin is sample high at the rising edge of the EN pin?

    Here are the following recommendations since the receiver doesn’t support ASSR.

    The DSI86’s ASSR will need to be disabled by making ASSR_CONTROL read/write instead of read-only. The first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:
    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

    Thanks,

    Zach

  • 0 in reply to Zach Dryer
    Prodigy 136 points

    Hello.
    Yes, I already have pull-up the TEST2 pin to VCCIO correctly.(And I checked the TEST2 pin level is "High".)
    I've understand how disable ASSR mode, and refered to "Script_NoASSR" sheet in the setting file below.

    e2e.ti.com/.../faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers


    As I wrote in previous reply,
    even though the setting contents are the same,
    there is a difference in results between manual input and continuous writing from FPGA.

    I don't understand why the difference between the two write methods causes a difference in results.


    Where do you think I should check?

    Thanks.

  • +1 in reply to Shinji Mada
    TI__Genius 13310 points

    Hello, 

    I need more context as to the difference between manual method and the continuous FPGA  method.

    Do you have other devices on the I2C bus? What value of the I2C resistors are you using?

    Are you using the same I2C rate for both manual and FPGA R/W speeds? 

    What link training method are you using? Have you tried another one and get the same problem?

    Thanks,

    Zach

  • 0 in reply to Zach Dryer
    Prodigy 136 points

    Hello.

    I'm very sorry.
    It was a simple mistake.
    I intended to have the same settings, but there was a difference.

    Question is over.
    Thank you for your reply to resolve some problems.