SN65DSI86-Q1: Monitor MIPI input data

KL

You can use the DSI86 status registers located at offsets 0xF0 thru 0xF8 as an indication of the MIPI interface status.

Addresses 0xF0 thru 0xF3 report errors associated with the DSI interface. Sometimes errors flags can be set at power-on or during start of the DSI stream. For this reason, it is recommended to clear flags by writing 0xFF and then reading back status flags. The bits which remain set are the errors which should be focused on. Typically errors set in these fields indicate signal integrity issues. Recommend verifying setup/hold meet DSI86 requirements. Also, adjustment of the RX EQ located at register offset 0x11 may help.

Address 0xF6 thru 0xF7 report errors associated with DSI to DP video timing. Typically, errors are set in these registers when video timing programmed into DSI86 doesn’t match timing received on the DSI interface. It is important the DSI86’s video registers located from 0x20 thru 0x3A match video timing used by the DSI source. The DSI86 will derive the DP timings from values programmed into these registers.

Thanks

David