The PHY has a 50Mhz input clock on the XI pin that is stable. I have backported the TI driver from 5.15 linux to 4.1 linux. All x_mmd routines that access the PHY registers were replaced with routines that use the MDIO bus to communicate. All read/write testing of registers successful and values are good.
When stopping in U-boot, the PHY is soft reset through the BMCR register. The PHY will successfully auto negotiate, and the ETH interface works fine.
Probing of the RX_CLK and TX_CLK pins shows a valid clock.
When the system boots, the MAC driver discovers the PHY and calls the driver reset function.
The TI driver uses the PHYRCR (0x1f) register to do a hard reset, and validates that the reset bit clears.
Afterwards, the RX_CLK and TX_CLK are idle. The PHY RX_CLK/TX_CLK signales are connected to a CYCLONE5 FPGA that needs these clocks active for its own reset functionality,
This initialization fails, and the ETH interface cannot be brought up.
I tried writing 0x0200 to BMCR to start auto negotiation but this has no effect on enabling the clocks.
What am I missing in the setup to get the RX_CLK/TX_CLK signals running again after the reset?
