I am asked following questions by customer. Please review and answer for each questions. This would be used for jig.
- GPO pin control with GPO_OUT_HIGH_CFG
I would like to use the GPO pin by switching between 3 states during operation: buffer Lo (sink), buffer Hi (source), and Hi-Z (Lo or Hi).
Specifically, with CFG=VDD, after initialization is complete (after the datasheet Fig. 8 flow), we are thinking of using it by repeating GPO_OUT_DATA write → GPO_OUT_HIGH_CFG rewrite → GPO_OUT_DATA write...
The data sheet Fig. 9 does not describe the flow for rewriting GPO_OUT_HIGH_CFG after operation starts, and I am concerned that GPO_OUT_HIGH_CFG is assumed to be used only during initialization.
Is it possible to use it as above?
- Logic high/low -level output current range
Regarding the value of logic high/low-level output current, for example, when VDDIO=1.8V, does it mean that the source/sink behavior of 4mA or more will deviate from the guaranteed range of VOH and VOL?
Also, when VIO = VDD = VDDIO = 1.8V, I would like to know about the impedance of the GPO pin at full buffer (approximately 100Ω, etc.).
