Hello Madam, Sir,
We found the rise/fall time of LVDS Data of DS90UB928 were faster than 0.26ns min. of LVDS spec, TIA/EIA-644-A, see Table.1, Fig.1 and Fig.2. Is there any way to make it slower? For example, to change to registry setting of DS90UB928 or DS90UB929?
Here is the display path of our system.
Intel Apollo Lake SoC -->(HDMI) --> DS90UB929TRGCTQ1 --> (FPD-LINK) --> DS90UB928QSQ/NOPB --> (LVDS) --> 10” LVDS panel
Thx!
Table.1
Fig.1
Fig.2
Hi Shu,
Thanks for your support.
Yes, we measured the LVDS directly at the output of the 928. See enclosures for the schematics and layout of 928/LVDS connector.
Furthermore, for the rise/fall time of 928 too fast issue, what do you think? When TI designs 928, what is the design criteria of rise and fall time?
Regards,
Eric Li
DS90UB928_schematics_20230313.pdf
Hi Eric,
Where is spec coming from? I cannot find the table in TIA/EIA-644-A.
Also as per the standard, the rise and fall times should be measured at 10%/90% basis and the provided scope does not look like it's measured with that same correlation, the yellow lines should be at 270mV and -270mV.
In addition for the 928 our spec just has the typical rise time characterized at 0.25ns with no minimum requirement. Please note that there needs to be an 100 ohm termination resistor at the end of the LVDS (receiver side ok) but I don't see it from the schematic or layout.
Best,
Shu
Hi Shu,
Thanks for your support.
TIA/EIA-644-A describes the electrical characteristics of Low-Voltage Differential Signaling (LVDS) Interface Circuits. The whole document should be able to be gotten from jedec.org if you have account. Above Fig.2 is part of TIA/EIA-644-A which describe the spec of rise/fall time should be 260ps and 0.3 tui and measured at 20%/80%. There has a TI document, slla038b: Interface Circuits for TIA/EIA-644(LVDS), mentions about TIA/EIA-644.
When we measured the waveform, we added the 100 ohm terminal resistors at the end of LVDS manually (CN6 of schematics), that is for sure.
Furthermore, as you mentioned, for 928, the typical rise/fall time is 0.25ns, max 0.5ns and no minimum requirement. For rise/fall time less than 0.25ns and no any adverse effect for adjacent signals, from point view of TI, what do you think about it?
Hi Eric,
What is the value of the VOD control register, are you able to observe any changes by changing this setting?
Furthermore, as you mentioned, for 928, the typical rise/fall time is 0.25ns, max 0.5ns and no minimum requirement. For rise/fall time less than 0.25ns and no any adverse effect for adjacent signals, from point view of TI, what do you think about it?
I will need to check in with our validation team on the characterization process and how that fits into the LVDS specs.
Best,
Shu
Hi Shu,
Thanks for your support.
The LVDS VOD control, bit[1:0] of Reg0x4B, was set at 0x01 (600mV differential). We ever set it at 0x00 (400mV differential) before, the rise/fall time was longer (~0.27ns) but the VOD was lower and too small (~200mV), see Table.1.
We were waiting for your check and further update.
Table.1
Regards,
Eric Li
