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Hi team,
My customer couldn't turn on the screen stably when using 941Splitter Mode in the early stage, but he can turn on the screen stably after configuring the 0x3E and 0x3F registers. The configuration parameters are as follows:
{0x3E 0x15},
{0x3F 0x7C},
{0x3E 0xB5},
At present, the customer's two registers are not well understood, and I hope BU can answer them. Will there be other problems with the above configuration?
Hi Alan,
These registers are used to configure the M and N values of the splitter PCLK. When splitter is enable, bits [4:0] of 0x3E and all of 0x3F are typically used in cases where they are splitting an asymmetric input, while bits [7:5] of 0x3E is used to enable the splitter clock as well as what clock source to use for the divider.
More information can be found in this App Note.
M and N config is purely dependent on the customers setup.
Thanks,
Ryan