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DS90UB947-Q1: 300KHz interval spurs

Ryan Wang
Expert 7435 points
Part Number: DS90UB947-Q1

Dear expert,

How to set internal oscillator frequency M/N for PCLK? I didn't see any register setting for it.

Thanks

  • 0
    TI__Guru** 107980 points

    Hello Ryan,

    Do you mean for using the Pattern generator? If yes, this can be done in the indirect registers as per this AppNote.

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 7435 points

    Hamzeh,

    NO. I don't mean for patgen. 

    I want to configure different internal clock frequency to replace external OLDI clock from SoC to confirm EMI issue.

    Now customer system is UB947->UB948. PCLK is 44MHz.

    They measured FPDLink signal at UB947 output. There are spikes every 300KHz across whole frequency.

    They tried external linear power to replace on board DCDC. The phenomenon is still there.

    "PCLK Auto" bit in 0x3 register is 1. Then they remove external OLDI clock from SoC to use internal clock. Then these 300KHz interval spurs are gone.

    But when they measure this 44MHz OLDI clock, they didn't see these 300KHz interval spurs.

    Is there any suggestion for this issue?

    Great thanks

  • +1 in reply to Ryan Wang
    TI__Guru** 107980 points

    Ryan,

    you can't configure the internal clock. It can be configured only for patgen use. So I recommend you use the patgen on the 947 side using the same pclk value and see if you still see these spurs.