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DS90UB953-Q1: deserializer GPIO triggers when serializer is digital reset.

Blessy Abraham
Prodigy 50 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: DS90UB960-Q1

Hi team, 

I am using deserializer - ds90ub960 & serializer - ds90ub953 for camera to processor communication. Please refer the below diagram for the connection information.

 

Whenever I do a digital reset of ds90ub953 i.e. 0x01 = 0x01, I get a pulse in either of the GPIO's (GPIO0 or GPIO1) of deserializer or sometimes both GPIO0 and GPIO1 of deserializer. This in turn is giving me an interrupt in the processor which is not the desired one. 

Can you help me with resolving this issue? 

  • 0
    TI__Expert 8030 points

    Hello,

    To better understand the behavior of that you are observing, I have the following questions:

    Can you please provide some more details about the type of pulse that is occurring whenever the device is reset? Is the voltage level of the GPIO pins initially at a logic high voltage level before a digital reset occurs? Does the voltage level of the GPIO pin then go to a logic low voltage level whenever a digital reset is performed? 

    Is there a pull up resistor connected to either the GPIO pins configured as inputs on the DS90UB953-Q1?

    Is there a pull up resistor connected to either the GPIO pins configured as outputs on the DS90UB960-Q1?

    Regards,

    Kenneth

  • 0 in reply to Kenneth Arnold
    Prodigy 50 points



    Attaching the probed data of the pulse from GPIO 0 and GPIO 1.

    The pulse width is in the range of nano seconds. Here, pulse width of GPIO0 is ~20ns and GPIO1 is ~60ns.

    The voltage level of GPIO0 and GPIO1 is low initially.

    There are no pull-up or pull-down resistors connected to the GPIO pins on serializer or deserializer. 

  • 0 in reply to Blessy Abraham
    TI__Expert 8030 points

    Hello,

    Thanks for providing more information. 

    One potential solution for this problem could be to disable GPIO 0 and GPIO 1 on the deserializer before the digital reset is performed. This way, a pulse would not be output from the DS90UB960-Q1 to the processor whenever the DS90UB953-Q1 is digitally reset. 

    To find the root cause of this pulse, I have a few more questions:

    -Were the pulse waveforms that you provided measured at a point between the processor and the DS90UB960-Q1?

    -Does a similar pulse occur at the GPIO pins of the DS90UB953-Q1? If a pulse does occur, does it match the behavior of the pulse that you observed on the output GPIO pins of the DS90UB960-Q1?

    To provide more feedback, I will also need to view a design schematic file that shows the connections of both the serializer GPIO pins and the deserializer GPIO pins. I sent you a friend request on E2E. If you accept it, you can then use the private message feature to send me your design schematic files. 

    Regards,

    Kenneth

  • 0 in reply to Kenneth Arnold
    Prodigy 50 points

    Hi Kenneth, 

    The pulse waveform is seen between the processor and the ds90ub960-Q1 and it is NOT seen on the GPIO pins of ds90ub953. 

    We are also seeing this issue in the TI-DS90UB960-Q1EVM board (HSDC011 REVB)

  • +1 in reply to Blessy Abraham
    TI__Expert 8030 points

    Hi Blessy,

    Thanks for providing additional information about your test results with the DS90UB960-Q1 Evaluation Module. 

    After speaking with other members of the team about this issue, I believe that the results you are observing for this configuration are expected.

    Whenever the DS90UB953-Q1 is digitally reset, the forward channel in the FPD-Link connection is effectively being removed. When this happens, any GPIO pins that are mapped to the forward channel are now left in an indeterminate state. In this state, the pin can take on any value, which can include the "pulse" behavior that you have observed in your test setup. 

    To prevent this pulse from being sent to the processor, I recommend that you manually define the output state of each GPIO pin as a logic low before you perform the digital reset. This can be done by first configuring Bits 7:5 in Register 0x11 and 0x10 of the DS90UB960-Q1 to output the value of GPIOx_OUT_VAL, and then setting Bit 1 in Register 0x11 and 0x10 of the DS90UB960-Q1 to '0'. Doing this for each GPIO pin will ensure that both GPIO0 and GPIO1 remain low while the DS90UB953-Q1 is being digitally reset. After the remote serializer is digitally reset, the GPIO pins of the deserializer will need to be remapped to the forward channel, so that they can be reconnected to the remote serializer GPIO pins.

    Locally configuring the GPIO pins such that they have a defined logic low state before the serializer is reset should prevent any pulses from being sent from the deserializer to the processor. 

    If you have any further questions, please let me know. 

    Regards,

    Kenneth