DP83TG720S-Q1: How to configure Analog Loopback With Inbuilt Data-Gen？

qidong liu

Part Number: DP83TG720S-Q1
Other Parts Discussed in Thread: DRA821

Hello
The phy chip model we use is DP83TG720S-Q1. Currently, the phy chip is already working properly. However, due to testing needs, we need to configure loopback for testing. The mode of loopback is Analog Loopback With Inbuilt Data-Gen. I configured according to the Table 7-2. Datapath BIST Programming of the datasheet. However, the registers corresponding to the Data Generator and Data Checker do not have any values. How should I configure registers to enable Analog Loopback With Inbuilt Data-Gen ? Can I configure a list of registers?

你好
我们使用的phy芯片型号是DP83TG720S-Q1。目前phy芯片已经可以正常工作了。但是因为测试需要，我们要配置loopback进行测试。loopback的模式是 Analog Loopback With Inbuilt Data-Gen。我按照datasheet的 Table 7-2. Datapath BIST Programming进行了配置。但是Data Generator和Data Checker对应的寄存器没有任何值。请问我应该如何配置寄存器来使能 Analog Loopback With Inbuilt Data-Gen？可以给一个寄存器配置列表吗？

over 2 years ago

0 Gerome Cacho over 2 years ago

TI__Mastermind 40275 points

Hello,

What do you mean by your quote:

qidong liu said:
However, the registers corresponding to the Data Generator and Data Checker do not have any values

According to table 7-2:

Reg 0x16 = 0x8

Reg 0x405 = 0x2800

Reg 0x619 = 0x557

Reg 0x624 = 0x55BF

Once these have been written, you can check using these registers:

Reg 0x620[1] write to '1'

Read Reg 0x602[7:0] for error number

Read 0x620[8] to confirm that data is coming and checker is locked.

Please note that some of these registers need extended register access.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1133146/faq-dp83tg720s-q1-how-to-read-or-write-registers-in-extended-register-space-of-ethernet-phy?tisearch=e2e-sitesearch&keymatch=extended%20register%20access#

Sincerely,

Gerome

0 qidong liu over 2 years ago in reply to Gerome Cacho

Intellectual 265 points

Hello Gerome,

Thank you for your reply.

Data Generator and Data Checker are always 0.

After configuring the register as you said, reads out that 0x620 is 0x0800 and 0x602 is 0x0000，BMCR is 0x4140.

thanks

0 Gerome Cacho over 2 years ago in reply to qidong liu

TI__Mastermind 40275 points

Hi,

I checked this out in the lab and it looks that everything is correct.

Script:

begin

001f 8000
0016 0008
0405 2800

0619 0557
0624 55BF
0620 0b02
end

0 qidong liu over 2 years ago in reply to Gerome Cacho

Intellectual 265 points

Hello Gerome,

After setting the registers in sequence, 0x620 is 0x0800。

What else are the troubleshooting directions？

thanks

0 Gerome Cacho over 2 years ago in reply to qidong liu

TI__Mastermind 40275 points

Hi,

I do not see extended register access in this script. Our program, USB2MDIO, is able to bypass this in the backend, but I do not see register 0xD/E pattern to access non-0x0-1F registers. Can you confirm you are accessing this? Can you also try this out if you have an EVM?

Sincerely,

Gerome

0 qidong liu over 2 years ago in reply to Gerome Cacho

Intellectual 265 points

Hi Gerome，

We do not have an EVM.
We have encapsulated the reading and writing of registers:
if( reg <= 0x1F )
devad = 0;
else if( reg < 0x1000 )
devad = MMD_CR_MMD1F_DEVID;
else {
devad = (reg>>12)&0xF;
reg &= 0xFFF;
}
if( 0 == devad ) {
status = EnetPhy_readReg(hPhy, reg, &data);
}
else {
EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_ADDR);
EnetPhy_writeReg(hPhy, PHY_MMD_DR, reg);
EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_DATA_NOPOSTINC);
status = EnetPhy_readReg(hPhy, PHY_MMD_DR, &data);
}
if (status == ENETPHY_SOK) {
data = (data & ~mask) | (val & mask);
if( 0 == devad ) {
EnetPhy_writeReg(hPhy, reg, data);
}
else {
EnetPhy_writeReg(hPhy, PHY_MMD_CR, devad | MMD_CR_DATA_NOPOSTINC);
EnetPhy_writeReg(hPhy, PHY_MMD_DR, data);
}}

thanks

0 Gerome Cacho over 2 years ago in reply to qidong liu

TI__Mastermind 40275 points

Hello,

Do you have link partner connected when this result is being run?

Could you try re-reading this register twice to see if it is being read too fast?

Sincerely,

Gerome

0 qidong liu over 2 years ago in reply to Gerome Cacho

Intellectual 265 points

Hi Gerome,

No partner linked.

I have tried writing and reading registers manually, and the values are the same.

It should not be a problem of reading too fast.

thanks

0 Gerome Cacho over 2 years ago in reply to qidong liu

TI__Mastermind 40275 points

Hello,

Is this occurring on multiple different boards?

Could you also please share the register 0x3 value?

Are you seeing traffic on the MAC lines and/or on the MAC coming from the PHY?

Could you also try digital loopback steps with PRBS packet steps and report result?

Sincerely,

Gerome

0 qidong liu over 2 years ago in reply to Gerome Cacho

Intellectual 265 points

Hi Gerome,

Sorry for the late reply.
All board phenomena are consistent, not a single board issue
The value of register 0x3 is A284.
Using ifconfig - v query on dra821, it can be seen that the input value of an0 has been increasing while the output remains unchanged
Both MAC packets and PRBS stream have been attempted but have not been successful.

Best Regards

0 Gerome Cacho over 2 years ago in reply to qidong liu

TI__Mastermind 40275 points

Hello,

To ensure same setup, are you writing anything else into PHY prior to analog loopback commands? You can see in my code, I reset the PHY to default settings via Reg 0x1F = 0x8000. Can you please try this at the beginning of your write sequence?

Regarding ifconfig -v query, I am not as familiar with this. However, you say that you have packets coming to MAC, while output remains unchanged. What does output mean in this case? Is MAC supplying packets to PHY also? If so, this should not happen.

Also please know that this datasheet has been updated to clean up this table in revision E.

Sincerely,

Gerome

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DP83TG720S-Q1: How to configure Analog Loopback With Inbuilt Data-Gen？