DP83825I: No power sequencing needed if RST_N is kept low?

Robert Finger

Part Number: DP83825I

Team,

In "Figure 1. Power-Up Timing" the sequencing requirement with VVDDIO first followed by VAVDD is shown. But chapter 9 says, no sequencing is needed if RST_N is used.

This is confusing, as the sequencing diagram anyhow shows that RESET_N should be low during power up.

Can you please clarify? In my use case VVDDIO is 1.8 V.

Thanks,
Robert

over 1 year ago

0 Gerome Cacho over 1 year ago

TI__Mastermind 31985 points

Robert,

Power supply recommendations should be followed if possible; where there are specific ramp times and analog supply lagging digital at most by 200ms. If this sequence cannot be met, hold the PHY in reset until all rails are good to go.

Sincerely,

Gerome

0 Robert Finger over 1 year ago in reply to Gerome Cacho

TI__Genius 16552 points

Hi Gerome,

Just to be sure: so the device should be kept in reset until both power rails are valid. And then, is there an additional reset pulse needed? Chapter 9 says "an external Reset (RST_N) is needed".

Thanks,
Robert

0 Gerome Cacho over 1 year ago in reply to Robert Finger

TI__Mastermind 31985 points

Robert,

An additional pulse is not needed as this holding that device in reset is that pulse. Once the signal is released, the device will begin reset sequence.

Sincerely,

Gerome

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DP83825I: No power sequencing needed if RST_N is kept low?