SN65DSI84: Display configuration and screen flicker during test pattern

Siddhi Naik

Prodigy 140 points

Part Number: SN65DSI84

Hello,

We are using the HDA1010WHPT-I-3GHI display along with SN65DSI84

Our DSI CLK is about 222.2MHz.

And using DSI Tuner we have configured following parameters. Are these configurations correct?

We use the test pattern config and see that the green and white lines are swapped compared to expected pattern as well as the flickers a bit.

Thanks in advance,

Sohil

over 2 years ago

0 Zach Dryer over 2 years ago

TI__Genius 13310 points

Hello, Sohil,

I cannot find a datasheet for HDA1010WHPT-I-3GHI. Why does your DSI Htotal differ from your LVDS Htotal? Also check your LVDS CLK and DSI CLK to make sure you are following the suggested CLK speeds.

However, you can look at https://e2e.ti.com/support/interface-group/interface/f/interface-forum/990480/faq-sn65dsi84-how-to-debug-flickering-video-with-sn65dsi83-sn65dsi84-and-sn65dsi85 for a starting place on how to start debugging these issues.

Thanks,
Zach

0 Siddhi Naik over 2 years ago in reply to Zach Dryer

Prodigy 140 points

Hi Zack,

I made a mistake in attaching the 1st page image it is as follows also I have attached the datasheet for HDA1010WHPT-I-3GHI

HDA1010WHPTI-3GH-I (1).pdf

I was trying config for both typical and max values as out DSI clock is around 222 MHz Hence the mixup

Thanks,

Siddhi

0 Zach Dryer over 2 years ago in reply to Siddhi Naik

TI__Genius 13310 points

Siddhi,

Please review the snapshots above based on your panel specifications.

Thanks,

Zach

0 Siddhi Naik over 2 years ago in reply to Zach Dryer

Prodigy 140 points

Hi Zach,

Thank you for the configurations.

Using the above configurations only the white color line changed to grey rest is same, flicker still continues

Thanks,

Siddhi

0 Siddhi Naik over 2 years ago in reply to Siddhi Naik

Prodigy 140 points

An update, we used external reference clock using a function generator of 23.7MHz and we get 71.1MHz on LVDS side, but the while line is still gray. Also We are unable to send any image onto frame buffer. Is this related to configuration as well?

Thanks,

Siddhi

0 Siddhi Naik over 2 years ago in reply to Siddhi Naik

Prodigy 140 points

Hi Zach,

So far we have tried to configure the DSI to LVDS using the DSI tuner app. We are using HDA1010WHPT-I-3GHI display.

Prior to configuration, we get the DSI clock frequency of about 222 MHZ based on frequencies defined in dtb and we are not sure if it's configured correctly.

Hence we wanted to isolate whether the issue is on dsi side or lvds side. So we selected the refclk option in the tuner and used an external reference clock of 23.7MHz on the Refclk pin (we had a max 25MHz function generator). We used a multiplier of 3 to get in the range of the display’s operational frequency of 71.1MHz on the LVDS side after following your suggested configurations.

Although the white line turned gray, the flickering has nearly stopped a few glitched can be seen from time to time. This seems that with Refclk input we do not get any flickering even though the original pattern vs our pattern has green and White colours swapped positions. We would like to understand if the attached waveforms and configurations we are doing are for DSI or should we modify something at dtb level.

Regards,

Siddhi

0 Zach Dryer over 2 years ago in reply to Siddhi Naik

TI__Genius 13310 points

Siddhi,

I am looking at what you have provided and will get back to you soon.

Thanks,

Zach

0 Siddhi Naik over 2 years ago in reply to Zach Dryer

Prodigy 140 points

Hi Zach,

While validating the initialization sequence as per the following link.https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85

We observe that our waveform do not match with the expected results.

Could you provide your feedback on the same

We have probed i2c clock, DSI clock, and enable and you can find the wavefroms as follow

Thanks,

Siddhi

0 Zach Dryer over 2 years ago in reply to Siddhi Naik

TI__Genius 13310 points

Hello, Siddhi,

Could you also provide screen shots of when your VCC goes high on the device?

Please ensure that you follow 7.4.3 Initialization Sequence. This sequence is required for proper operation of the device

After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state

0 Siddhi Naik over 2 years ago in reply to Zach Dryer

Prodigy 140 points

Hi Zach,

It's a bit difficult to capture waveforms at power up since the DSI to LVDS chip configuration happens after each power up, so if we try capturing waveforms at power up we don't think that the IC would be functioning as desired in an unconfigured state.

Regards,

Siddhi

0 Zach Dryer over 2 years ago in reply to Siddhi Naik

TI__Genius 13310 points

Hello, Siddhi,

Once the DSI84 enable signal goes high, it does not look like the DSI CLK lanes are in the HS state from the scope shots. Looks like the amplitude of the DSI CLK increases only after enable goes low.

Additionally, the DSI data lanes MUST be driven to LP11 state could you show me a DSI Data lane scope shot as well?

Thanks,

Zach