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DS90UB960-Q1: Behavior when FS_CTL FS_SINGLE bit is toggled

Kevin Stone
Prodigy 20 points
Part Number: DS90UB960-Q1

Hi,

I was curious about the exact behavior of the FS_SINGLE bit in FS_CTL (0x18). When it's set to 1 does that immediately drive the FrameSync signal high? or is there a delay? Does FS_INIT_STATE, FS_GEN_MODE, or FS_HIGH_TIME_x/FS_LOW_TIME_x affect the behavior of FS_SINGLE? I'm seeing an unexpectedly large delay (around 17ms) between setting FS_SINGLE to 1 and receiving the mipi sof packet for the camera image. I'm trying to figure out if that delay is due to serdes (ub960 + ub953) behavior or camera behavior (ov10650). Thanks!

  • +1
    TI__Genius 16230 points

    HI Kevin,

    To generate eh single pulse, program hte FS_CTL option and FS_LOW_TIME and FS_HIGH_TIME for the expected pulse.  After configuring the operation mode, also set the FS_SINGLE nit in the FS_CTL register. 

    The pulse should have minimal delay after executing the command. Have you tried probing the FS_SYNC signal? You can probe the I2C and the FS_SYNC to see the delay. At this time I believe that your imager is causing the delay.

    Glenn 

  • 0 in reply to Glenn Uranga
    Prodigy 20 points

    Thanks for the response. I was able to confirm the delay is due to some undocumented camera behavior, and the ub960 pulse is working as expected.