DS90UB953-Q1: How to configure the UB953 and UB960

Hi Kenneth Arnold,

Thank you for your help!

Do I need to configure the CSI format on both the UB953 and UB960? 

Can the UB953 output signals without configuring the UB953's CSI format?

How is the value of NUM_CBARS selected when configuring PGEN_CFG? 

How is the value of PGEN_BAR_SIZE calculated?

DTS configuration for UB953:

#define SER_MODEL ub953
#define SER_NODE CONCAT_3(SER_MODEL,_,PORT_IDX)
#define SER_NODE_NAME CONCAT_3(SER_MODEL,@,SER_ADDR)
#define SER_PATH CONCAT_5(DES_PATH,/link@,DES_LINK,/,SER_NODE_NAME)
#define DES_LINK_NODE CONCAT_3(DES_NODE,_link, DES_LINK)

#define SER_GPIO_NODE CONCAT_3(SER_MODEL,_gpio_,PORT_IDX)

&DES_LINK_NODE {
    SER_NODE: SER_NODE_NAME {
        compatible = "d3,ub953";
        status = STR(STATUS);
        physical-addr = <0x18>;
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <HEX_PREFIX(SER_ADDR)>;
        csi-lane-count = <4>;
        csi-continuous-clock = <1>;
        i2c-voltage-sel = <0x0>;

        SER_GPIO_NODE: SER_GPIO_NODE {
            compatible = "d3,ub953-gpio";
            status = "okay";
            gpio-controller;
            #gpio-cells = <2>;
            ngpios = <4>;
        };
    };  
};

The register values for UB953 are as follows:

Device ID Register(0x00): 0x30

General Configuration(0x02): 0x72

Forward Channel Mode Selection(0x03): 0x4b

General Status(0x52): 0x45

DTS configuration for UB960:

#define DES_NAME ub960
#define DES_PATH CONCAT_3(\
I2C_BASE_PATH,/,\
CONCAT_3(DES_NAME,@,DES_ADDR))

#define DES_NODE CONCAT_3(DES_NAME,_,DES_ADDR)

/ {
        CONCAT_2(i2c@,I2C_ADDR) {
                /* Deserializer */
                DES_NODE: DES_NAME@DES_ADDR {
                        status = STR(STATUS);
                        compatible = "d3,ub960";
                        reg = <HEX_PREFIX(DES_ADDR)>;
                        iovdd-supply = IOVDD_SUPPLY;
                        avdd-supply = AVDD_SUPPLY;
                        pdb-gpios = RESET_PIN;
                        csi-lane-count = <CSI_LANES>;  // CSI_LANES is 4
                        csi-tx-speed-mbps = <1600>;
                        csi-continuous-clock = <1>;

                        frame-sync-mode = <8>;

                        frame-sync-high-time-us = <15000>;
                        frame-sync-low-time-us = <35000>;

                        #address-cells = <1>;
                        #size-cells = <0>;
                        CONCAT_2(DES_NODE,_link0): link@0 {
                                reg = <0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                        };
                        CONCAT_2(DES_NODE,_link1): link@1 {
                                reg = <1>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                        };
                        CONCAT_2(DES_NODE,_link2): link@2 {
                                reg = <2>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                        };
                        CONCAT_2(DES_NODE,_link3): link@3 {
                                reg = <3>;
                                #address-cells = <1>;
                                #size-cells = <0>;
                        };
                };
        };
};

The register values for UB960 are as follows:

Device ID Register(0x00): 0x64

RX_PORT_CTL Register(0x0c): 0xf

RX_PORT_STS1 Register(0x4d): 0x13

BCC_CONFIG Register(0x58): 0x5e

SER ID(0x5b): 0x30

SER ALIAS ID (0x5c): 0x00

PORT_CONFIG Register(0x6d): 0x3c

What I can confirm is that there is a signal output from the radar, but I can't read the data on the Soc.

Which of my configurations is error? Or am I missing a configured register?

Hi Wenqiang,

I'm currently looking into this, and will provide an update within the next 24 hours.

Regards, 

Kenneth

Hi Wenqiang,

Thank you for your patience. 

For the DS90UB953-Q1 register values that you have provided, I have the following questions:

- I see that you have configured this device for CSI-2 continuous clock. Does this CSI-2 clock configuration match the CSI-2 clock configuration of the AWR2243?

For the DS90UB960-Q1, I have the following questions:

-Do the CSI-2 clock and data lane configurations of the DS90UB960-Q1 match the CSI-2 clock and data lane configurations of the SOC? 

-Have you used an oscilloscope/probe to confirm if CSI-2 data is being output on either of the CSI-2 ports of the DS90UB960-Q1?

From the register data that you have shared, it looks like the link between the DS90UB953-Q1 and the DS90UB960-Q1 is successful. Therefore, data should have no problems being transmitted over the link. To further understand if there are any potential configuration issues with either device, I need to examine the configurations of all registers. Could you please export and send the register data of all registers for both the DS90UB960-Q1 and the DS90UB953-Q1?

Regards,

Kenneth

Hi Kenneth Arnold,

Thank you for your reply!

The 4 GPIO ports of the DS90UB953-Q1 are not connected. 

The clock mode of the forward channel of the DS90UB953-Q1 is "Non-Synchronous Internal Mode".

DS90UB953-Q1 registers:

30 00 72 4b 00 18 21 28 fe 1e 10 7f 7f 01 f0 00
00 00 00 00 00 20 18 3c 80 62 62 62 00 00 00 00
00 00 00 00 00 02 00 00 67 33 01 00 00 00 00 00
00 20 09 04 00 10 00 64 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20 c0 45 00 00 00 00 00 07 07 07 02 00 00 00 00
00 2a 00 10 0f 8b 00 64 00 00 00 00 00 00 00 00
00 00 25 00 00 00 00 00 00 00 e4 00 00 00 00 00
00 00 00 00 00 00 90 00 00 00 00 00 05 00 00 00
32 e3 64 01 00 00 00 00 00 00 03 02 00 00 00 0f
00 0d 0e 0d 0e 10 42 10 10 10 03 01 00 00 00 00
00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5f 55 42 39 35 33

DS90UB960-Q1 registers:

64 00 1e 40 c0 01 00 fe 1c 10 7a 7a 0f 00 02 ff
00 00 00 00 00 00 00 00 01 61 a8 e3 dd 00 04 0c
00 03 00 0f 00 00 00 00 00 00 00 00 00 00 00 00
00 00 01 43 00 00 00 00 00 00 00 00 00 00 00 00
00 a9 71 01 00 00 20 00 00 00 00 12 01 03 14 37
14 00 00 03 00 00 00 00 5e 00 00 30 00 30 50 00
00 00 00 00 00 80 c0 00 00 00 00 00 00 3c 8a 88
2b 2c 00 00 24 17 70 c5 00 01 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
01 16 01 16 27 8d 27 a6 00 00 00 00 00 00 00 00
00 00 00 00 00 1b 00 00 00 00 00 00 00 00 00 00
00 0f 00 08 25 00 18 00 9c 33 83 74 80 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 43 94 03 60 f2 00 02 00 01 00 10 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00

Regards,

Wenqiang Zhou

Hi Wenqiang,

Thank you for sending register data. I will review the register data and let you know if I identify any register configurations that could be causing the issue that you are seeing. 

To determine why data cannot be read on the SoC, I also recommend that you use first try and see if data can be read by the SoC whenever it is generated by the deserializer pattern generator. Doing this will help us determine if the issue is being caused by the configuration of the serializer/image sensor, or the configuration of the deserializer/SoC. For more information about how to use the pattern generator feature of the DS90UB960-Q1, I recommend that you refer to Section 7.5.12 of the DS90UB960-Q1 datasheet. For an example pattern generation script, you can also refer to Section 7.1.11 of this application note: 

https://www.ti.com/lit/an/snla267a/snla267a.pdf

The application note specifically refers to the DS90UB954-Q1, but some of the principles relating to the pattern generator can also be applied to the DS90UB960-Q1. 

Regards,

Kenneth

Hi Kenneth Arnold,

Thank you for your reply!

I used the following function to set the registers of the UB960.

static int ub960_colorbar_pattern(struct ub960 *self)
{
int err = 0;

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_CTL, 0x0));

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x01)); // PGEN_CTL
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x01)); // enagle PGEN

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x02)); // PGEN_CFG
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x24)); // Send Color Bar Pattern, 4 Color Bars, 4 bytes

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x03)); // PGEN_CSI_DI
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x2A)); // RAW8:0x2A RAW16:0x2E

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x04)); // PGEN_LINE_SIZE1
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x17)); // 0x1770=6000
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x05)); // PGEN_LINE_SIZE0
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x70)); //

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x06)); // PGEN_BAR_SIZE1
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x05)); // 0x05dc=1500
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x07)); // PGEN_BAR_SIZE0
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0xdc)); //

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x08)); // PGEN_ACT_LPF1
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x00)); //
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x09)); // PGEN_ACT_LPF0
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x24)); // 0x24=36

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x0a)); // PGEN_TOT_LPF1
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x00)); //
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x0b)); // PGEN_TOT_LPF0
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x24)); // 0x24=36

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x0c)); // PGEN_LINE_PD1
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x0B)); //
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x0d)); // PGEN_LINE_PD0
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x93)); //

TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x0e)); // PGEN_VBP
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x00)); //
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_ADDR, 0x0f)); // PGEN_VFP
TRY(err, regmap_write(self->map, UB960_REG_IND_ACC_DATA, 0x00)); //

TRY(err, regmap_write(self->map, UB960_REG_FWD_CTL1, 0xF0));
TRY(err, regmap_write(self->map, UB960_REG_CSI_CTL1, 0x01));

return err;
}

The values of the four registers are：

CSI_PORT_SEL=0x1, FWD_CTL1=0xf0 CSI_PLL_CTL=0x8 CSI_CTL=0x1

However, the oscilloscope still does not detect signals at CSI0_CLKN and CSI0_CLKP of the UB960.

What is the reason for this?

Hi Wenqiang, 

1. Can you double check your CSI-2 forwarding settings? In your last message using patgen, you say that CSI_CTL Reg 0x33 = 0x01 (no CSI continuous clock, no CSI skew calibration). However in your register dump, you have Reg 0x33 = 0x43 (CSI continuous clock, CSI skew calibration). Can you double check 0x33 and the CSI transmitter speed in 0x1F to make sure it is aligning with your SOC and imager? 
2. In your 960 register dump, it looks like you have CSI_PLL_CTL Reg 0x1F = 0x0C. Can you try setting 0x1F = 0x08 so that the REF_CLK_MODE bit is 0?
3. In your 960 register dump, I am seeing a buffer overflow error in register 0x4E. This means the 960 is receiving more video input than it can output. Are all of the imagers sending the same video to the deserializer? Can you provide the following imager information so I can check the bandwidth? 
   1. Horizontal Active Pixels = ?
   2.  Vertical Active Lines = ?
   3. Vertical Total Lines (Vertical Active + Vertical Blanking) = ?
   4. Frame Rate = ?
   5. Bits-Per-Pixel = ? 
   6. Continuous Clock Mode in the 960 = Yes or no? 
   7. Data rate per lane on the 960 = 1.6Gbps?
   8. Active CSI-2 data lanes on the 960 = 4 lanes? 
   9. Forwarding Mode = Round Robin

Regards,

Cindy

Hi Cindy Li，

I wrote the Pattern Generator code for testing by referring to section 7.6.4 of the DS90UB953-Q1 datasheet.

The output signal of the DS90UB953-Q1 is still not detected with an oscilloscope.

Do I still need to make special settings?

Hi Wenqiang,

Have you tried enabling the pattern generator on the 960 instead to see if the SOC can read it? Before running patgen, please make sure to configure the CSI-2 settings as per datasheet guidelines in section 7.5.12: 

In your patgen script, it looks like your line size is 6000 bytes and total lines per frame is 36. Is this intentional? 

Regards,

Cindy

Hi Cindy Li,

    Now I don't have any custom parameters, I just use the parameters from the datasheet "Code Example for Pattern Generator".

    The UB953 has no signal output.

    The UB960 also has four registers CSI_PORT_SEL, FWD_CTL1, CSI_PLL_CTL and CSI_CTL configured, but also no signal output.

Hi Wenqiang,

Only the 960 will have a CSI-2 output if you enable patgen on either the 960 or 953.

• Are you using an oscilloscope to measure the output signal, or are you reading from the SOC?
• Can you please send me the script you are using for configuring patgen? The previous patgen script you sent was not using the values in the Code Example for Pattern Generator in Section 7.5.12.4.
• Can you also send a 960 register dump when patgen is on?

Regards,

Cindy

• The output signal from the UB960 is not detected by the oscilloscope and the data is not read on the Soc.

• static int pattern_generator(struct regmap *map)
  {
  int err = 0;

  TRY(err, regmap_write(map, 0xB0, 0x0));

  TRY(err, regmap_write(map, 0xB1, 0x01)); // PGEN_CTL
  TRY(err, regmap_write(map, 0xB2, 0x01)); // enagle PGEN

  TRY(err, regmap_write(map, 0xB1, 0x02)); // PGEN_CFG
  TRY(err, regmap_write(map, 0xB2, 0x33)); // Send Color Bar Pattern, 4 Color Bars, 4 bytes

  TRY(err, regmap_write(map, 0xB1, 0x03)); // PGEN_CSI_DI
  TRY(err, regmap_write(map, 0xB2, 0x24)); // 0x24:RGB888 0x2A:RAW8 0x2E:RAW16

  TRY(err, regmap_write(map, 0xB1, 0x04)); // PGEN_LINE_SIZE1
  TRY(err, regmap_write(map, 0xB2, 0x0f)); //
  TRY(err, regmap_write(map, 0xB1, 0x05)); // PGEN_LINE_SIZE0
  TRY(err, regmap_write(map, 0xB2, 0x00)); //

  TRY(err, regmap_write(map, 0xB1, 0x06)); // PGEN_BAR_SIZE1
  TRY(err, regmap_write(map, 0xB2, 0x01)); //
  TRY(err, regmap_write(map, 0xB1, 0x07)); // PGEN_BAR_SIZE0
  TRY(err, regmap_write(map, 0xB2, 0xe0)); //

  TRY(err, regmap_write(map, 0xB1, 0x08)); // PGEN_ACT_LPF1
  TRY(err, regmap_write(map, 0xB2, 0x02)); //
  TRY(err, regmap_write(map, 0xB1, 0x09)); // PGEN_ACT_LPF0
  TRY(err, regmap_write(map, 0xB2, 0xd0)); //

  TRY(err, regmap_write(map, 0xB1, 0x0a)); // PGEN_TOT_LPF1
  TRY(err, regmap_write(map, 0xB2, 0x04)); //
  TRY(err, regmap_write(map, 0xB1, 0x0b)); // PGEN_TOT_LPF0
  TRY(err, regmap_write(map, 0xB2, 0x1a)); //

  TRY(err, regmap_write(map, 0xB1, 0x0c)); // PGEN_LINE_PD1
  TRY(err, regmap_write(map, 0xB2, 0x0c)); //
  TRY(err, regmap_write(map, 0xB1, 0x0d)); // PGEN_LINE_PD0
  TRY(err, regmap_write(map, 0xB2, 0x67)); //

  
  TRY(err, regmap_write(map, 0xB1, 0x0e)); // PGEN_VBP
  TRY(err, regmap_write(map, 0xB2, 0x21)); //
  TRY(err, regmap_write(map, 0xB1, 0x0f)); // PGEN_VFP
  TRY(err, regmap_write(map, 0xB2, 0x0A)); //

  return err;
  }

• UB953 Enable Pattern Generator

Values of UB960 register:

64 00 1e 40 d0 01 00 fe 1c 10 7a 7a 04 00 02 ff
00 00 00 00 00 00 00 00 80 61 a8 e3 dd 00 04 04
b0 03 00 04 00 00 00 00 00 00 00 00 00 00 00 00
00 00 01 43 01 01 00 00 00 00 00 00 00 00 00 00
00 a9 71 01 00 00 20 00 00 00 00 12 24 83 04 62
8f 00 00 04 00 00 00 00 5a 00 00 30 84 a8 50 00
00 00 00 00 00 a8 c4 00 00 00 00 00 00 7c 8a 88
ab ac aa 02 d0 0f 00 c5 00 01 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
01 2f 00 00 ff ff 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 1d 00 00 00 00 00 00 00 00 00 00
1c 13 1f 08 25 00 18 00 9c 33 83 74 80 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 43 94 17 60 f2 00 02 00 01 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00

Values of UB953 register:

30 00 73 4b 00 18 41 28 fe 1e 10 7f 7f 06 34 00
00 00 00 00 00 20 18 3c 80 62 62 62 00 00 00 00
00 00 00 00 00 02 00 00 67 33 01 00 00 00 00 00
00 20 09 04 00 12 00 64 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20 c0 45 00 00 00 00 00 07 07 07 00 00 00 00 00
00 2a 00 10 0f 8b 00 64 00 00 00 00 00 00 00 00
00 00 25 00 00 00 00 00 00 00 e4 00 00 00 00 00
00 00 00 00 00 00 90 00 00 00 00 00 07 00 00 00
32 e3 64 01 00 00 00 00 00 00 06 08 00 26 00 10
00 11 10 0e 0f 10 42 10 10 10 03 01 00 00 00 00
00 0f 0a 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5f 55 42 39 35 33

• UB960 Enable Pattern Generator

Add the following configuration:

err = regmap_write(info->ub960, 0x32, 0x01); // CSI_PORT_SE val: 0x01, 0x12
err += regmap_write(info->ub960, 0x20, 0xF0); // FWD_CTL1
err += regmap_write(info->ub960, 0x1f, 0x08); // CSI_PLL_CTL
err += regmap_write(info->ub960, 0x33, 0x01); // CSI_CTL1

Values of UB960 register:

64 00 1e 40 c0 01 00 fe 1c 10 7a 7a 04 00 02 ff
00 00 00 00 00 00 00 00 80 61 a8 e3 dd 00 04 08
f0 03 00 04 00 00 00 00 00 00 00 00 00 00 00 00
00 00 01 01 01 00 00 00 00 00 00 00 00 00 00 00
00 a9 71 01 00 00 20 00 00 00 00 12 24 83 04 74
f5 00 00 04 00 00 00 00 5a 00 00 30 84 a8 50 00
00 00 00 00 00 a8 c4 00 00 00 00 00 00 7c 8a 88
ab ac aa 02 d0 0f 00 c5 00 01 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 1d 00 00 00 00 00 00 00 00 00 00
00 0f 0a 08 25 00 18 00 9c 33 83 74 80 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 43 94 17 60 f2 00 02 00 01 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00