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DS90UB926Q-Q1: 0x3B Register confirm

Hale Tan
Expert 3770 points
Part Number: DS90UB926Q-Q1
Other Parts Discussed in Thread: ALP

Hi team,

I want to make sure what is the meaning of DS90UB926Q-Q1 0x3B register. The customer found that when it displays abnormally, this register has changed. Could you provide some information about 0x3B register?

  • 0
    TI__Mastermind 38955 points

    Hi Hale,

    What value are you getting for this register? What is happening to the display, I.E Discoloration, artifacts, lines? Are there any other registers changing in correlation with this issue?

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    TI__Expert 3770 points

    Hi Ryan,

    I will share some useful information via email.

  • 0 in reply to Hale Tan
    TI__Mastermind 38955 points

    Hi Hale,

    Register 0x3B is the AEQ status register.

    Looking at the information you sent me, it seems like the register is capping out at its maximum value, indicating that it may be a link margin issue.

    If possible, could your customer run a MAP test through our MAP tool in ALP and send the results? This E2E should detail how to update ALP if they do not see this feature.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    TI__Expert 3770 points

    Hi Ryan,

    As you said, it seems like the register is capping out at its maximum value, indicating that it may be a link margin issue. What's the maximum value of AEQ status register. Could you show more details about this register? Does the whole 0x3B register stand for its maximum value? If it is capping out at its maximum value, what is the lock pin status? Could I tell if the system has a link margin issue by lock pin? 

  • 0 in reply to Hale Tan
    TI__Mastermind 38955 points

    Hi Hale,

    For register 0x3B, the EQ Status takes up bits [5:0], that means that when the equalizer is set to its maximum settings by the AEQ, that register should read 0x3F, which is the case as you indicated with the information sent. This can mean that the equalizer is being set to max settings by the AEQ to try to compensate for transmission loss and is unable to reduce the jitter enough, indicating that there is a link margin issue. The other bits of register 0x3B are reserved, and should be 0 at default.

    Since the video is still visible while AEQ is maxed out, per the example image you sent, Lock should still be high. While LOCK can be used to indicate issues in the video stream or connection, it cannot be used to explicitly indicate link margin issues.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    TI__Expert 3770 points

    Hi Ryan,

    Do you have more material about AEQ to share with the customer?

  • 0 in reply to Hale Tan
    TI__Mastermind 38955 points

    Hi Hale,

    More information can be found in the DS90UB928 datasheet: www.ti.com/.../DS90UB928Q-Q1

    Aside from that, additional information is proprietary and not meant to be shared to customers.

    Thanks,

    Ryan