DP83TG720S-Q1: power up timing and reset timing question

zouyongchang

Part Number: DP83TG720S-Q1

HI TEAM

I have some power up questions for DP83TG720S

(1) for the VDDA power up timing, the minimum value of T5.1 is 0.5ms，however we measured it 0.039ms，so what risk will this cause？

I looked over all the power up timing questions， some expert indicate that it will cause some POR problem，and should HW RESET the phy to solve the problem？does it can solve my risk？

（2） in the power up timing ，there is no reset signal ，so ，when powered up， when can the reset singal can be low or high？

（3）in reset timing，we can get the T6.1, I wanner kown how long would it be take in the red circle part of reset timing in the followed figure

hope for your answer，thanks

over 2 years ago

0 Gokul Koraganji over 2 years ago

TI__Mastermind 19250 points

Hi Yong,

39us is too fast a ramp for VDDA. This ramp can trigger supply ESD protection and can lead to having huge leakage from supply on some devices.
The leakage can cause LDO supplying the PHY to dip by a huge amount. Multiple power-up and downs might cause a damage to the device too.
I recommend moving the ramp time to 500us.

zouyongchang said:
in the power up timing ，there is no reset signal ，so ，when powered up， when can the reset singal can be low or high？

During power-up, RESET_N can be either high or low. There is no restriction.

zouyongchang said:
in reset timing，we can get the T6.1, I wanner kown how long would it be take in the red circle part of reset timing in the followed figure

As I mentioned above, it can be high or low. The timing when you want to reset the PHY can be user's preference.

--
Regards,
Gokul.

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DP83TG720S-Q1: power up timing and reset timing question