TS3DV642: Interfacing Two Switches for Single 4 Lane MIPI CSI,

sakthi vel

Part Number: TS3DV642

Hello There,

We are currently designing a project that requires configuring different MIPI sources on a single 4-lane MIPI-compatible processor. Depending on the use case, we will switch to different ports. As shown in the image, Port B is selected in both switches (one switch port B is connected with 2 Lane MIPI + Clock, another switch port B is connected only with 2 Lane MIPI). Will splitting and connecting the MIPI through a switch cause any issues? like an imbalance of delay mismatches in between the traces? If so, how can we get past it?

Thanks,
Sakthivel

over 2 years ago

0 David (ASIC) Liu over 2 years ago

TI__Guru**** 180021 points

Sakthivel

You would have propagation delay across the part and inter-pair skew across the channel. I would not recommend routing Port B across two TS3DV642. How many lanes does Port A need?

Thanks

David

0 sakthi vel over 2 years ago in reply to David (ASIC) Liu

Prodigy 160 points

David,

Port A needed 2 lanes of MIPI on both switches.

Is there any other alternate way available to achieve the above-mentioned MIPI configuration?

Can you suggest any 3:1 MIPI Mux which is available in TI ?

Thanks,

Sakthivel

0 David (ASIC) Liu over 2 years ago in reply to sakthi vel

TI__Guru**** 180021 points

Sakthivel

You can use the TS3DV642-Q1 HDP/CEC and SDA/SCL for the Port A 2 lanes. HDP/CEC and SDA/SCL have the same electrical characteristic as the main port links, we just named them differently for HDMI implementation purpose.

Thanks

David

0 sakthi vel over 2 years ago in reply to David (ASIC) Liu

Prodigy 160 points

David,

Our requirement is to have 4 lanes of MIPI (4 differential data pairs and 1 differential clock pair), so totally 5 nodes of high-speed differential line muxing, but in the case of the part suggested, "TS3DV642-Q1," it can control only 4 differential lanes. So could you please suggest any part with which we can control five differential data sets?

Thanks,
Sakthivel

0 David (ASIC) Liu over 2 years ago in reply to sakthi vel

TI__Guru**** 180021 points

Sakthivel

So if I understand the system correctly, you would need 7 channels (5 for Port B and 2 for Port A)?

The HDP/CEC and SDA/SCL are the same as the four high speed differential lane, this will give you total six high speed differential lanes, is this enough for your need?

Thanks

David

Interface

Interface forum

TS3DV642: Interfacing Two Switches for Single 4 Lane MIPI CSI,