SN65DSI85-Q1: How to use INT

Harry Shin1

Expert 6740 points

Part Number: SN65DSI85-Q1

Hello Team,

My customer is asking how to use INT of device.

Before go to customer, I want to make sure with you my understanding.

Could you pls help answer several questions as below??

1) How to enable DSI_IRQ??

I understand that it is 0xe0 bit0 and also enabled 0xe1/e2 for IRQ items. Am I correct?

2) How to clear DSI_IRQ??

I understand that 0xe5/e6 shows error flag and write 1 on those registers can clear it. then IRQ would be high again. Am I correct??

3) Do you have any recommendation to enable IRQ feature in power up sequence??

I understand IRQ is high in no error flag status while IRQ is low if error happen. is this correct??

if so, IRQ can be enable immediately after done power up sequence if no error flag. What do you think about this??

Thank you.

over 2 years ago

0 Zach Dryer over 2 years ago

TI__Genius 13310 points

Harry,

The SN65DSI85-Q1 device provides an IRQ pin that can indicate when certain errors occur on DSI. The IRQ output is enabled through the IRQ_EN bit (CSR 0xE0.0). Individual error conditions for DSI Channel A are enabled through the Channel A Error Enable bits (CSR 0xE1.7-2). Individual error conditions for DSI Channel B are enabled through the Channel B Error Enable bits (CSR 0xE2.7-2). The IRQ pin is asserted when an error occurs on DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a 1 to the corresponding error status bit.

Thanks,

Zach

0 Harry Shin1 over 2 years ago in reply to Zach Dryer

TI__Expert 6740 points

Hello Zach,

Thanks for reply.

but I am still waiting your answer for question #3.

Could you pls help answer this to customer??

Thank you.

0 Zach Dryer over 2 years ago in reply to Harry Shin1

TI__Genius 13310 points

Harry,

You will setup the IRQ registers with the rest of the CSR register per the initialization sequence per the 8.3.2 Initialization Setup section of the datasheet.

When enabled by the IRQ_EN, the IRQ output is driven high to communicate IRQ events. The errors reported by registers 0xE5 and 0xE6 are indicated when a bit is set to 1.

Thanks,

Zach

+1 David (ASIC) Liu over 2 years ago in reply to Zach Dryer

TI__Guru**** 176571 points

Harry,

The error flags reported during power-up are false, you need to clear them before enable the IRQ.

Thanks

David

0 Harry Shin1 over 2 years ago in reply to David (ASIC) Liu

TI__Expert 6740 points

Thank you Zach, and David~

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SN65DSI85-Q1: How to use INT