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TPD1E01B04-Q1: Anti-pad design application notes

Part Number: TPD1E01B04-Q1
Other Parts Discussed in Thread: TPD1E01B04

Hi Expert,

My customer using TPD1E01B04-Q1  as the ESD protection for FPD-LINK

From customer perspective, on the ESD protection of the high-speed interface, the parasitic capacitance will affect the TDR.

If it is convenient for you, would you mind sharing some technical application notes of ESD Anti pad?

Thanks a lot for your warm help!

  • Hi Imelda,

    All diodes will have a parisitic capacitance that will affect signal integrity, however if you choose an ultra low capacitance diode like TPD1E01B04 the signal attenuation is minimal for signals up to 20 Gbps. 

    I wasn't able to find any application notes that only cover anti-pads however they are mentioned briefly in several app notes. 

    High-Speed Interface Layout Guidelines (Rev. J)

    FPD-Link High Speed Design and Channel Requirements

    Regards,

    Sebastian 

  • Hi Sebastian,

    Thanks a lot for your warm help!

    Here are other ESD suppliers  provide the curve of ESD influence of Mark4 TDR. Do we have such technical documents? 

  • Hi Imelda.

    We don't have any such technical documents using a TDR. For signal integrity purposes we conduct an insertion loss test with our low cap. diodes. The insertion loss graph shows the energy that a signal loses as the signal frequency on the input increases. Devices with higher capacitance will cause a higher insertion loss. 

    The general rule of thumb is to only protect signals with speeds below the -3dB point on the insertion loss graph.

    Also TDR measurements will be affected by the PCB layout which will be different from customer to customer. If we conducted TDR measurements on a board with different trace sizes or different stackups, the results might not be easily replicated on the customer PCB. 

    Regards,

    Sebastian