DP83640: Link and Activity LED Status in case of Software is not running yet

Hi Doner,

I am not sure if I understand your question completely, you are seeing an LED link up when you plug in ethernet cable to the PC before programing anything on FPGA right?

If my understanding is correct, this situation is expected. LED link up indication are mainly displaying ethernet cable side instead of the MAC side or (MII communication). The PHY should link up automatically without any programing requirement

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Regards,

Hillman Lin

Hi Hillman Lin,

Thank you for your reply. 

Hillman Lin said:

I am not sure if I understand your question completely, you are seeing an LED link up when you plug in ethernet cable to the PC before programing anything on FPGA right?

Yes. Situation was exactly this. 

After that, we just realized that PHY was not in Reset state when power-up, due to RESET_N input pulled up on the board. After changing RESET_N input with a pull-down on the board, We have kept the PHY in the reset state at power up. Now is Link & Activity LEDs are not light up when we plugged to cable in case of FPGA is not programmed yet, as expected.  

But now, after we programmed FPGA and just only released (means drive High) the RESET_IN input of PHY by software, again Link & Activity light up (cable plugged of course). We haven't accessed and configured the PHY from the MDIO interface yet, or any software still doesn't work. We just drive the RESET_IN input high. 

In order to understand the reason for this traffic when the software is not running yet, we captured the MII interface between PHY and FPGA by adding ILA debug core. Shortly after RESET_IN released (nearly 400 us later), we saw that PHY started driving RX_DV ( receive data valid) high and sending random size of frames to the FPGA. Activity was due to this random size frames. We dont interpret this situation why PHY sending this random data to FPGA on the MII interface, just after releasing the RESET_IN, even if PHY is not configured from MDIO interface yet and any application software is not running yet. Who might be generating this random data? Is it the PHY itself or the other node in the LAN?

Best Regards,

Hi Doner,

May I ask what application are you trying to perform? A block diagram would help.

• RX_DV driven high is most likely cost by strapping which is in the datasheet section 5.5.
• There will be activity between MII communication every time you power up and reset.

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Regards,

Hillman Lin

Hi,

It is an EtherCAT application. I use DP83640 PHY for EtherCAT Master on my board. We try to communicate with an EtherCAT Slave. Just we add ILA core on the MII interface between PHY & FPGA. And we observed below cases: 

Please note that, we did not configure the PHY via MDIO. PHY is working as its default power-up configurations. 

• Master side cable unplugged. After we released RESET_IN input of PHY, we did not see any random data on the RX_Data lines of the MII. 
• Master side cable plugged, but slave side unplugged. After we released RESET_IN input of PHY, we did not see any random data. 
• Master side cable plugged and slave side plugged. Master and Slave is connected to each other now. After we released RESET_IN input of PHY (we did not configure the PHY through MDIO, we use PHY as its default power-up settings), we saw some random data on the RX_Data lines of the MII. All data is started with mostly 0x55 (sometimes started with 0x5555) and ended with 0x55 ( and sometimes with not x55). Size is not standard. There are various frames with different sizes. RX_DV is driven high and sometimes later driven low. Not everytime High. 

What can be the reason of the these random data ? Actually these random data is broken the our EtherCAT line. 

Best Regards,

Hi Doner,

If possible, could you draw a block diagram for more clarification?

If my understanding is correct, it seems like there is some signal coming from the slave side of the EtherCAT that DP83640 is picking up the signal. May I ask what is the PHY you are using for the slave side?

Are you using one master and one slave or daisy chain for your EtherCAT application?

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Thank you,

Hillman Lin

Hi Hillman Lin,

Please find attached a diagram of setup. 

I dont know what PHY is used inside the slaves. We have one Master and below Slaves. But note that, we have not started to Master functionality yet. Before it, in order to be sure EtherCAT bus is stable and have a valid physical connection, at first, we send some frames periodically and expect to receive them back the same frames. At the beginning of the test, just after releasing Reset of the PHY, before we send these periodic frames, we just quickly received those random bytes. RX_Data valid line became high before TX_EN. So, we immediately received something after Link established. They are such a random bytes, not even standard Ethernet frames. They have various sizes around sometimes 18 bytes sometimes 200 bytes. 

Connector is not RJ-45 on the board. It is a board-to-board connector. 

Best Regards

Hello,

I work alongside Hillman. He will be able to continue this discussion starting next week as TI is on Good Friday/Easter Holiday.

Sincerely,

Gerome