I have board set up for FPGA MAC <-> PHY0 <-> CAT5 <-> PHY1 <-> FPGA MAC for 1GB transmission
Both MACs are sending the same test data every 50 usec interval. I have validated on MII -> Analogback with no issue.
Once i remove loopback and switch to MDI i can also see transmit / receive working OK, but at some point i believe one of the PHYs enters a strange state that continuously sends garbage data on the RGMII RX side.
TX side of PHY appears to stop working in this state as well
When in this error state, RGMII RX side gets stuck repeatedly sending 0xE0E0. The data set i am sending is a pattern of A5A5 or 5A5A, so im not entirely sure if this is a hint to the actual issue or a byproduct of the data i am sending.
This error state is held until i unplug the CAT5 cable and ressetablish the connection. From there it will reenter tis error state after 5-20 minutes.
LED0 is setup to blink when there is transmit/receive activity. I
LED1 is setup to turn on when ther eis transmit/receive error.
When this error state occurs: Both PHYs' (PHY0 and PHY1) LEDs show
: LED 0 is no longer blinking, but always on. (autnegotiation OK but no transmission)
LED1 led is constantly on
I have a few suspicions as to why this could be:
1. Issues on magnetics side / cabling (unlikely since i have multiple boards and can see the same issue on each)
2. MDIO r/w is set up to read right after RX is received on RGMII. Does the DP83867CR have any restrictions of read/write of MDIO PHY registers during rx/tx?
3. PHY clock integrity? (unlikely since XI is generated from mac and is repeatedly on few different MAC -> PHY interfaces on multiple boards
Thank you
