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TRS208: ESD test condition - TRS208IDWR

kato makoto
Prodigy 90 points
Part Number: TRS208

I have contacted the CSC group but could not get the answer from them. (CS1675169)
But,they suggested the question ask to E2E was supported.

In the TRS208IDWR datasheet, the ESD test conditions for the HBM model are described as ±15000V at each Dout and Rin terminals.

Is it correct to assume that the other terminals (C1+, C1-, C2+, C2-, V+, V-) also pass the ±15000V ESD withstand voltage condition?

Please let me know it.

Please share the evidence document if available

Best regards;
Makoto KATO

  • 0
    Guru 284090 points

    When the datasheet says that the DOUT and RIN pins have ±15 kV protection, then this does not imply anything about the other pins. Only these two RS-232 pins are supposed to go to a connector where a human can touch them.

    The other pins have some ESD protection, but only enough to handle smaller ESD events that happen during automatic assembly.

  • 0 in reply to Clemens Ladisch
    Prodigy 90 points

    I think these other terminal is supply pin, It's have not ESD withstand problem.

    In this time,we have to answer to custmer all terminal withstand value to Custoner adation document request..

  • 0 in reply to kato makoto
    Guru 284090 points

    The datasheet just says "standard ESD protection". This probably implies 500 V HBM and 250 V CDM, which is the JEDEC minimum for manufacturing with a standard ESD control process.

  • 0 in reply to kato makoto
    TI__Mastermind 46857 points

    Hi Kato,

    Clemens is correct - the only ESD ratings we have are for the RS-232 IO pins - which is +/-15kV. The other pins have ESD protection, but it isn't explicity rated

    From Datasheet:

    TI TRS208 devices have standard ESD protection structures incorporated on the pins to protect against electrostatic discharges encountered during assembly and handling. In addition, the RS-232 bus pins (driver outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures were designed to successfully protect these bus pins against ESD discharge of ±15 kV when powered down.

    Most likely this implies the JEDEC minimum - but it isn't explicitly mentioned - so there is no additional ratings given - but the minimums Clemens shared are the most likely values.

    Best,

    Parker Dodson